February 11, 2008 -- Synfora, Inc. today announced the availability of PICO Extreme, a breakthrough in algorithmic synthesis technology that enables the implementation of larger and more complex sub-systems using a recursive system composition methodology based on Synfora’s TCAB technology. PICO Extreme allows familiar design styles, reduces runtime and achieves unprecedented quality of results including reduced power.

Synfora’s PICO platform automatically creates complex hardware sub-systems (application engines) from sequential untimed C algorithms. Tools based on the PICO platform allow designers to explore programmability, performance, power, area and clock frequency. In addition, tools developed with the PICO platform technology will reduce time to market by eliminating months of manual RTL design and providing a comprehensive and robust verification and validation environment including SystemC TLM support and automatic RTL testbench creation.

PICO Extreme’s recursive system composition methodology is enabled by tightly coupled accelerator blocks (TCABs) that let users designate parts of their algorithms as custom building blocks. These application-specific building blocks are C procedures that can be designed and verified standalone and then automatically integrated and scheduled as if they were primitive computing elements. In addition, TCABs can be composed of TCABs providing recursive composition of blocks to an arbitrary depth. This composition methodology improves the ability of the compiler to find better optimization, which improves performance and reduces area. With PICO Extreme, building hardware with pre-created blocks reduces the total runtime. Such a mixed bottom-up, top-down approach is very natural for designers.

"Algorithmic synthesis has been proven on small parts of an algorithm. To capture substantial algorithms and still achieve excellent results and fast run-times, a breakthrough was needed," said Simon Napper, President of Synfora.

Along with the TCAB technology, PICO Extreme also delivers the following capabilities for reduced power and ease of integration into the SOC:

An advanced clock gating scheme that enables the designer to gate the clock of a complete processing function (loop nest) as a single entity halting any activity within the processing function (including the clock tree) and only requiring one clock gating cell. The ability to extract and export mapping information that enables C-RTL equivalence checking tools to verify the equivalence between PICO-generated RTL and C. This information includes design latency/throughput, bit-accurate mapping of external C variables and stream functions to RTL block interfaces including scalar, stream and memory ports, and bit-accurate mapping of internal C variables to RTL wires, registers and memory objects. An option to create OCP-IP compliant host interface to ease integration into the rest of the SOC.

Pricing and Availability