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 Category: News: News Archive 2008: Wednesday, May 22, 2013
Denali's Blueprint Employed by Atheros to Enhance SOC Design Productivity and Enable Rapid IP Reusability  
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March 27, 2008 -- Denali Software, Inc. today announced it has licensed its Blueprint product to Atheros Communications, Inc., a leading developer of advanced wireless and wired solutions. Atheros will employ Blueprint's SOC design tools in developing the company's Radio-on-Chip for Mobile (ROCm) solutions and other products. The Denali Blueprint Compiler was specifically designed for hardware and software engineers to generate and manage all control registers throughout the design process, to speed pre-silicon validation, maintain architectural quality and thus, increase productivity.

Denali Blueprint is a SystemRDL compiler that enables a system-level approach to automating specification, view generation, and management of control registers for IP and SoC design. Blueprint will generate necessary outputs and views for design, verification, documentation, software development, post silicon debug and even enables early software development with SystemC Transaction Level Models. Blueprint guarantees interoperability with other EDA tools by inputting and outputting IP-XACT and SystemRDL formats.

"The Blueprint system-level design tool significantly reduces integration time, helps ensure consistency and eases propagation of changes throughout the design and verification process," said Steve Padnos, Methodology Architect for Atheros. "Atheros selected Denali because it provides an integral and valuable platform solution for SoC design."

Go to the Denali Software, Inc. website for details.

E-mail Denali Software, Inc. for more information.

Read more about
Denali Software, Inc.
on SOCcentral.com


Keywords: Denali Software, compilers, IP, intellectual property, cores, SystemC, transaction level modeling, transaction-level modeling, TLM, ASIC design, EDA tools,
578/25305 3/27/2008 2617 213


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