June 5, 2008 -- CLK Design Automation, Inc. has announced the Amber FX Analyzer as the industry’s first transistor statistical static timing analysis (TSSTA) solution. The Amber FX Analyzer integrates transistor-level static timing analysis (STA) and statistical static timing analysis (SSTA) with high accuracy transistor models that can be generated in hours using the latest process data from semiconductor foundries. Chip designers can now validate the performance and margins of leading-edge designs with more accurate statistical analysis and the most current manufacturing information right up to tape-out.

Amber FX is built on top of the Amber Analyzer, introduced in May 2007. It merges the performance of the Amber fully threaded, incremental analysis architecture with the accuracy of a new generation FX transistor model (FXM). The result is near Spice-level accuracy for timing delay and process variance, both of which are critical factors in the transition to 45 and 40-nm semiconductor processes. Amber FX is immediately available in two complementary modules, Amber FX Transistor STA and Amber FX Transistor SSTA, and is supported in the TSMC Reference Flow 9.0.

"Amber FX is the first STA and SSTA solution that combines performance, accuracy, and variance-aware timing in the same analysis," said Isadore Katz, President and CEO of CLK Design Automation. "Every other solution is a compromise. You can look at variance, but without accuracy, or visa versa — all with painfully slow results. Amber FX provides near-Spice accuracy for delay and variance combined with threaded performance. Amber FXM libraries are the only solution, other than Spice itself, which can deliver the latest data from the foundry to the designer the very same day."

Highly accurate transistor modeling

Manufacturing variance is one of the biggest barriers to successful adoption of advanced 45-nm and 40-nm process nodes. Although the expectation is that these nodes will deliver much better speed and power at a lower cost per die, traditional corner-based timing closure methodologies are much too pessimistic and make timing closure very difficult. Statistical timing tools and new library formats such as CCSM and ECSM are supposed to address these problems. However, these tools and models are slower than their predecessors, and generating libraries can take weeks, causing them to be out of sync with the latest foundry data.

Amber FX removes these barriers with a FX transistor model that captures delay and variance directly from Spice, the foundry Spice model, and the Spice netlists for each of the cells. The Amber FXM library is a cell-level library that includes all of the transistors and parasitics for each cell. Amber FXM has been qualified with TSMC 65-nm and 40-nm libraries using Berkeley Spice and HSpice for characterization. FXM is an extension to the Liberty format and addresses a large number of known accuracy problems in existing Liberty, ECSM, and CCSM libraries. It handles a wide range of high-risk timing behaviors that are not properly modeled by other timing solutions, such as multiple input switching, non-linear input slopes, voltage drop, functional noise, etc.

In addition to the FXM model, Amber FX’s unique approach to TSSTA is enabled by its fast Spice analysis engine and architectural-level integration with the Amber platform for a seamless flow from STA through SSTA. This provides both Amber FX STA and SSTA users with all of the Amber performance and capabilities, including 10X speed-ups via threading and 100X throughput improvements for incremental operations, multi-mode/multi-corner analysis and debug, and signal integrity analysis.

Amber FX Transistor STA is used for block and full-chip transistor timing and signal integrity analysis. It uses the FXM model to perform STA with traditional corners for very high accuracy timing, and allows users to combine non-linear delay models with transistor models. Amber FX Transistor SSTA is used for path-based TSSTA with the FXM model. Corners are replaced with a statistical distribution for the timing, which represents the potential manufacturing variance as tracked and analyzed by the foundry. Users first complete a baseline static timing run and then select a set of paths for full transistor-level SSTA. The nominal delay and variance of these paths is then recalculated using the FXM model and delay calculator. For the purposes of reporting, the variance is treated as a normal distribution so timing can be assessed at multiple points.

Availability and Pricing