Page loading . . .

  
 Category: News: News Archive 2008: Saturday, May 25, 2013
Calypto, Forte Collaboration Results in Advanced SystemC Design Flow  
 Printer friendly
 E-Mail Item URL

October 23, 2008 -- As the result of more than three years of collaboration, Calypto Design Systems, Inc. and Forte Design Systems, Inc. have created an advanced SystemC design flow encompassing verification and implementation that provides consumer and multimedia electronics companies with improved productivity and design quality.

The seamless integration of Calypto’s SLEC System-HLS formal verification software and Forte’s Cynthesizer SystemC synthesis offers a complete SystemC to register transfer level (RTL) design flow. This advanced system-level solution has been proven by one of Japan’s largest integrated device manufacturers (IDMs) to support the complexity and capacity requirements of multi-million gate system-on-chip (SOC) designs.

Both products have been extensively tuned on numerous SystemC designs to satisfy sophisticated user requirements, such as custom interface specifications, external memory interfaces and fixed point datatypes. The advanced SystemC design flow enables users to specify and verify SOC functionality, communication and timing at the system level. SLEC verifies the equivalence of two SystemC models during system-level model refinement and comprehensively verifies the RTL code generated from Cynthesizer.

"High-level synthesis continues to provide a significant time-to-market advantage for design teams around the world," says Sean Dart, Forte’s president and CEO. "Coupled with sequential logic equivalence checking, designers can further improve their productivity and confidence using industry standard SystemC in their ESL design flow."

About SLEC

SLEC System-HLS verifies the RTL code generated from high-level synthesis (HLS) tools and is tightly integrated into HLS design flows by automating functional verification setup and supporting HLS language extensions. SLEC System-HLS verifies SystemC and RTL designs without the need for writing testbenches or running simulation. SLEC System-HLS is part of Calypto’s proven SLEC product family that also includes SLEC System, SLEC RTL and SLEC CG.

About Cynthesizer

Forte’s Cynthesizer delivers production quality RTL in one tenth of the time of hand-coded RTL designs, improves results, and eliminates downstream timing closure problems. Cynthesizer uses a high-level SystemC description to give designers the ability to build designs with custom interfaces and challenging architectural requirements not possible with other C-based products. Cynthesizer can automatically retarget designs to new speeds and process technologies and supports a level of reuse that is impossible in RTL.

Go to the Calypto Design Systems, Inc. website to find additional information.

E-mail Calypto Design Systems, Inc. for more information.

Read more about
Calypto Design Systems, Inc.
and
Forte Design Systems, Inc.
on SOCcentral.com


Keywords: Calypto Design Systems, Forte Design Systems, formal verification, SystemC synthesis, equivalence checking, ASICs, ASIC design, EDA tools,
578/27173 10/23/2008 2696 231


Designer's Mall
0.46875



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.578  0.53125