October 28, 2008 -- Cadence Design Systems, Inc. today announced that Legend Silicon Corp. has taped out a 90-nm design by leveraging the Cadence low-power solution to achieve first silicon success. Legend Silicon has selected Cadence as its primary EDA supplier for 65- and 45-nm designs, and will adopt the complete Cadence low-power solution.
With Cadence software, Legend Silicon taped out a challenging, multi-million gate 90-nm DTV design, which is now in volume production. As a result, Legend Silicon continues to offer leading-edge digital television products to its customers.
"Leveraging Cadence design, verification and implementation technologies, Legend Silicon is able to beat an aggressive design schedule and achieve first silicon success," said Dr. Lin Yang, the CTO of Legend Silicon. "By selecting Cadence as our primary EDA vendor for 65 and 45 nanometers and collaborating closely together, we will be able to maintain and sharpen our competitive edge in DTV and wireless fields, and provide better solutions within a shorter timeframe."
As the primary EDA supplier, Cadence will provide Legend Silicon with advanced EDA technologies for 45/65-nm low-power hierarchical flow. Legend Silicon will also adopt the Common Power Format (CPF)-based Cadence low-power solution, consisting of Incisive Enterprise Simulator, Encounter Conformal Low Power, Encounter RTL Compiler global synthesis, Encounter Digital Implementation System, and Encounter Power System.
Go to the Cadence Design Systems, Inc. website to find additional information.
