October 30, 2008 -- Cadence Design Systems, Inc. announced today that its test technologies have enabled Ltd. to cost-effectively produce high-performance LSI devices in volume with the lowest number of test escapes or defects achieved by Hitachi to date. By combining Cadence Encounter Test pattern-fault modeling with the state-of-the-art test pattern generation, compression technology and diagnostics, Cadence helps Hitachi ensure that these complex, high-performance LSI devices work as designed.
By combining Cadence's pattern fault modeling technology, SDF-based dynamic test generation, and OPMISR+ compression with Hitachi's test methodology, the two companies produced test vector compression results exceeding 300X. This matches industry compression requirements set for 2011, according to an ITRS industry survey published in 2007. In addition, the test coverage results for single-stuck-at-fault, delay-based and bridge fault exceeded Hitachi's requirements.
Combined with the Cadence diagnostic solution, the fault modeling and compression technologies result in faster yield ramps and more accurate and efficient vector sets than previous solutions. The increased accuracy leads to fewer test escapes, eliminating the need for time-consuming iterative debug and refinement loops to achieve high-quality test patterns.
"Through the Cadence Encounter Test pattern fault model and advanced test compression technology, we were able to achieve better test quality and meet our test cost requirements," said Toru Hiyama, General Manager, Hardware Monozukuri Division at Hitachi. "Our requirements were extremely aggressive, with challenges requiring advanced knowledge and leading technology capabilities, so we were really happy when the Encounter Test team was able to come through."
Go to the Cadence Design Systems, Inc. website to find additional information.
