November 14, 2008 -- Microtronix announced today that it has updated its high-performance line of multi-port SDRAM memory controller intellectual property (IP) cores to support the growing demand for next generation Altera Stratix III and Arria GX family of field programmable gate array (FPGA) devices.
To improve performance of the memory controller IP cores, the internal structure was redesigned to improve clock distribution networks and incorporate new architectural features available in Stratix III devices. These design changes improved timing closure and boosted DDR2 memory performance from 333MHz in a Stratix II to over 400MHz in a top speed grade Stratix III device.
Microtronix IP cores target SDR, DDR, Mobile DDR and DDR2 memory devices. They support Altera GX device families.
Availability
Microtronix cores are currently available for immediate sale. The standard license includes one year of maintenance updates.
An OpenCore Plus evaluation license is available to allow engineers to simulate the behavior of a Microtronix IP core within the targeted system, verify in-circuit the functionality of the design, and evaluate its size and speed quickly and easily.
Go to the Microtronix website to find additional information.
