December 16, 2008 -- Sundance has extended its partnership with Cadre Codesign, a specialist provider of IP and embedded FPGA design solutions, to deliver Cadre’s CT-JPEG04 core across a range of it’s modular DSP FPGA multiprocessor hardware solutions. Based on the JPEG ISO/IEC IS 110918-1 standard image-compression algorithm, the core compresses images of 1280x1024 pixels resolution at a rate of 500frames/sec and can sustain an input of one 8-bit pixel every 660MHz. This level of performance makes the solution ideally suited to applications where images are either analyzed on the fly or stored for later reference and analysis.

The Cadre Codesign core significantly outperforms standard off-the shelf JPEG cores that can typically sustain inputs of 4-MByte (64Kx64K images) frames at 30 frames per second and generate outputs of 122MBps. Provided with a ModelSim evaluation model the core will be initially available on Sundance’s Digital Video Infrastructure Platform (DVIP) that offers developers a complete, integrated solution for digital video development.

Built on Sundance’s modular and scalable multiprocessing concept, the DVIP leverages the performance and flexibility of two TI TMS320C6455 digital signal processors (DSPs) and a TMS320DM642 DSP-based digital media processor. The 1-GHz C6455 DSPs allow multiple processors to be connected via a Serial Rapid I/O (SRIO) interface and the DVIP incorporates Xilinx Virtex-4 FX60 FPGAs that are the implementation target for Cadre’s CT-JPEG04 core.

The modular architecture of the DVIP lets developers increase the processing performance in the field and add one of more than 40 additional variant modules that support the Sundance TIM (Texas Instruments Module) standard. As this standard is open-domain, it is also possible to integrate proprietary solutions. Design support is provided via 3L’s Diamond multiprocessor tool-suite that provides a highly automated development flow from concept through to applications running in multiprocessor hardware and Code Composer Studio from TI.

Pierre Popovic, Cadre Codesign’s President commented, "A key issue facing developers who use conventional systems is storage of the 524-MBpsc (monochrome) or 1.535-GBps (color) outputs generated by today’s high performance cameras, and this is compounded by bus technology that struggles to sustain more than 250 MBps. By marrying our CT-JPEG04 core with FPGA technology we provide an optimal compression solution that overcomes the bus bottleneck and storage problem."

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