SOCcentral: How to Design 65-nm FPGA DDR2 Memory Interfaces for Signal Integrity (EE Times Programmable Logic Designline 21590)

Category: Magazine & Journal Articles Online: Article Archive 2007:

Thursday, May 23, 2013

How to Design 65-nm FPGA DDR2 Memory Interfaces for Signal Integrity

Publication: EE Times Programmable Logic Designline
Contributor: Xilinx, Inc.

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January 24, 2007 -- This article presents practical techniques for incorporating "correctness by design" in DDR2 interfaces, from a signal integrity (SI) perspective, using the current generation of available design tools. Some common DDR2 design errors are analyzed, as well as the tradeoffs between some popular design alternatives.

By David Banas. (Banas is a senior staff applications engineer in the Advanced Products Division at Xilinx, Inc.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the EE Times Programmable Logic Designline website.

Read more about
Xilinx, Inc.
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Keywords: EE Times Programmable Logic Designline, Xilinx, signal integrity, FPGAs, field programmable gate arrays, embedded memory, EDA tools,

579/21590 1/24/2007 8360 625

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