February 5, 2007 -- Compile time for large designs has been a major bottleneck since FPGAs were first created. Reducing compile time offers a large benefit to users as their designs can be turned around quickly by analyzing and fixing failures and in turn improving time to market. Yet compile time remains an issue because as FPGA densities increase, designers are targeting these devices with designs that are more complex. Some of today's designs, provide as much functionality as two small FPGA devices, a small ASIC and an FPGA device, an individual ASIC or FPGA device, or an ASSP device did only a few years ago. Increasing the amount of complex logic on the device increases compile time. Addressing these issues with parallel compilation as a way of improving compile times is the most efficient methodology available.
By Ajay Jagtiani. (Jagtiani is a Product Planning Engineer at Altera Corp.)
This brief introduction has been excerpted from the original copyrighted article.