May 14, 2007 -- The growing demand for cheap consumer wireless applications calls for unprecedented levels of integration. Huge digital IPs, such as microprocessors, digital signal processors, or encryption engines, are being assembled together with analog blocks " e.g. power supply control, data conversion " and radio-frequency (RF) " LNA, VCOs, mixers. The former, aka the aggressor, generates lots of interfering noise, which gets disseminated through the entire system to finally degrade the operation of the most sensitive circuitry (the victim).
The entire electrical signal integrity (ESI) mechanism is very complex. It affects digital operation through IR drop, crosstalk and delay, as well as analog and RF. For the latter, the impact is rather more complicated as very small noise level will produce dramatic influences at any time, and not only in the neighborhood of specific signal transitions as occurs in the digital domain.
In summary, noise impacting analog and RF victims is produced by circuits manipulating large electrical signals at high frequencies. These aggressors are any combination of digital, analog or RF functions drawing significant amounts of current on the power supplies which, because of the various physical interconnect and package parasitics involved, result in considerable supply bounce.These parasitics also prevent a perfect collection of all the noise from the aggressors to off-chip, and the remaining noise gets propagated through a combination of substrate, interconnect and package parasitics. Noise injection happens across a wide range of various mechanisms, conductive through substrate biasing contacts, capacitive from source-drain junctions or metal capacitances, as well as well-substrate junctions. The noise disseminating across the whole system is further filtered when transferred through the RC substrate coupled to the RLC parasitics from both interconnect and package.
Among all the challenges to address ESI impact on analog and RF victims, modeling noise generation and injection is particularly tricky. The issue is to collect the many power supply and substrate currents in both time and frequency domains.
By François Clement. (Clement is the CTO at Coupling Wave Solutions.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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