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 Category: Magazine & Journal Articles Online: Article Archive 2007: Wednesday, May 22, 2013
The Incredible Journey of an 800-ps Period  
Publication: EE Times Programmable Logic Designline
Contributor: Xilinx, Inc.
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June 13, 2007 -- The size of one bit period at 1.25Gbps is 800ps, the data rate where even an interface with LVDS signaling probably cannot withstand all the sources of uncertainty in the journey from transmitter to receiver. Like the yellow-brick road in the movie The Wizard of Oz, the data path itself appears quite simple, but the hazards along the way are reminiscent of the fabled lions, tigers, and bears of Oz. In fact, the outcome is quite certain: our 800-ps period will not survive the journey — not without a little help.

By Greg Burton. (Burton is senior applications engineer for the advance products division at Xilinx, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Programmable Logic Designline website.

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Xilinx, Inc.
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Keywords: EE Times Programmable Logic Designline, Xilinx, low-voltage differential signaling, LVDS, FPGAs, field programmable gate arrays,
579/23142 6/13/2007 6180 427


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