| Designing DDR3 SDRAM Controllers with Today's FPGAs by Xilinx, Inc. in EE Times Programmable Logic Designline |
December 12, 2007 -- The recently introduced DDR3 SDRAM technology paves the way to higher data rates (from 800 Mbps to 1600 Mbps) and provides higher performance for many systems that depend on data, video, or packet processing.
In the c ... read more |
| Applying FPGAs in System-Critical Automotive Electronics by Actel Corp. in EE Times Automotive Designline |
December 12, 2007 -- Automotive manufacturers have long desired a reprogrammable technology able to be applied in a single platform targeted at multiple product models, with the flexibility to adapt and change during lengthy product lifecycles. ... read more |
| Applying Constrained-Random Verification to Microprocessors by Synopsys, Inc. in EE Times EDA Designline |
December 10, 2007 -- Constrained-random verification (CRV) offers a highly effective way to deal with the challenges of microprocessor verification. These verification challenges are overwhelming for many reasons: complex instruction sets, multi ... read more |
| Employ the Proper Flash Memory in Your Design by Silicon Storage Technology, Inc. (SST) in EE Times Embedded |
December 10, 2007 -- In their search for the perfect "universal memory," designers of embedded systems are like characters from the play Waiting for Godot. They're waiting for an off-stage character, "Godot," to come on stage, meanwhile speculat ... read more |
| Combining C and Assembly in DSP Applications by CEVA, Inc. in EE Times Signal Processing DesignLine |
December 10, 2007 -- As DSP processors become more powerful and compiler optimization techniques improve, the once common trend of writing DSP applications solely in assembly has withered away. Today, almost every DSP application is comprised of ... read more |
| Convert an FPGA to a Gate Array at Project Start by NEC Electronics America, Inc. in Electronic Engineering Times (EE Times) |
December 7, 2007 -- A successful semiconductor product often goes through a field-programmable gate array (FPGA)-to-gate array conversion as an afterthought. But what happens if this step is taken with forethought? Considering the gate array opt ... read more |
| Choosing the Right Industrial Control and Acquisition Hardware: FPGAs vs. PLCs vs. Custom Hardware by National Instruments Corp. in EE Times Industrial Control Designline |
December 7, 2007 -- It's a challenge every design engineer faces. For some it is merely a nuisance, but for others it can be a sleep-depriving exercise in frustration. Choosing the right hardware platform for industrial and control applications ... read more |
| Partitioning Applications Across Multiple Cores by Freescale Semiconductor, Inc. in Electronic Engineering Times (EE Times) |
December 7, 2007 -- The multi-core processors used today for networking equipment commonly target enterprise-level access routers, but the ones being marketed today offer much more than just layer-2 and layer-3 routing. Many higher-layer service ... read more |
| Using DFM Routing to Impact Design Performance and Yield by Pyxis Technology, Inc. in EE Times EDA Designline |
December 4, 2007 -- There are have been numerous papers written on the techniques that can be employed during integrated circuit (IC) design to achieve better overall manufacturability and yield. These design-for-manufacturing (DFM) techniques h ... read more |
| Case Study of a Complex Video System-on-Chip by CoWare, Inc. in Electronic Engineering Times (EE Times) |
December 3, 2007 -- The efficient design of complex, multimedia-intensive, heterogeneous multiprocessing (HMP) system-on-chips (SoCs) for inclusion in HDTVs and related consumer-oriented systems presents a daunting array of challenges. A collabo ... read more |
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