| Rethinking the System Design Process by Mirabilis Design, Inc. in EE Times EDA Designline |
July 23, 2007 -- The system design process can incorporate linear thinking, parallel thinking, or both, depending on the nature of the anticipated system, subsystem, or element of a subsystem. The structure, composition, scale, or focal point of ... read more |
| Compiler Optimization for DSP Applications by CEVA, Inc. in EE Times Signal Processing DesignLine |
July 23, 2007 -- As DSP processors become more and more powerful, the portion of code that can remain at the C level increases. However, compilers cannot produce optimized code without assistance from the programmer. To maximize the performance, ... read more |
| Is FPGA a Simpler Puzzle for ASIC Designers? by EDN Magazine |
July 19, 2007 -- Over the last 10 years, FPGA vendors have made great strides in overcoming the shortcomings of FPGAs and taking share from the ASIC market. In the late 1990s, FPGA vendors increased the capacity of their devices to rival midsize ... read more |
| Autovectorization for the GCC Compiler by Embedded Microprocessor Benchmark Consortium (EEMBC) in EDN Magazine |
July 19, 2007 -- With all of the mobile electronic devices available today, engineers are constantly seeking ways to make them smaller and more efficient. One way to accomplish this goal is to compress any data that must be stored or transmitted ... read more |
| Interface Chips: Between Logic and a Hard Place by EDN Magazine |
July 19, 2007 -- Logic signals have fallen from the 15V of the old CMOS 4000 series to 5V TTL (transistor-to-transistor logic) to modern CMOS levels of 3.3, 2.7, and 1.8V. Advanced processes use digital logic that operates at 1V or lower, althou ... read more |
| How to Enable Microsoft Office and Visio for RTL Design by Mentor Graphics Corp. in EE Times Programmable Logic Designline |
July 18, 2007 -- Microsoft Office tools, and in most cases Visio, are ubiquitous in the Windows environment. So, it is not surprising that tools such as Excel, Word, PowerPoint, Outlook, and Internet Explorer have found their way into the RTL de ... read more |
| Abstraction Levels and Hardware Design by Forte Design Systems, Inc. in EE Times EDA Designline |
July 17, 2007 -- Design of anything, from an ERP application to an embedded software system to a hardware device to a mechanical object, is done at some level of abstraction. Simply, a level of abstraction is the vocabulary that the designer use ... read more |
| ZigBee Emerges by Analog Devices, Inc. (ADI) in EDN Magazine |
July 13, 2007 -- In today's consumer market, two of the most prevalent local-area wireless technologies are Wi-Fi and Bluetooth. For connectivity between laptops, cell phones, and a variety of other handheld devices, these protocols make us wond ... read more |
| Getting Back to Basics with Planning, Metrics, and Management by Cadence Design Systems, Inc. in EE Times EDA Designline |
July 13, 2007 -- The verification problem gets more difficult every day and the industry continues to meet the challenge with ever more innovative tools that mostly address specific issues we face. Meanwhile, as an industry executive, do you kno ... read more |
| How to Implement a Compact, Cost-Effective, and Low-Power Ethernet-to-Network Processor Bridge by Lattice Semiconductor Corp. in EE Times Programmable Logic Designline |
July 11, 2007 -- As carriers and cable providers begin rolling out triple-play and VoD services to their customers, OEMs are increasing their development efforts to roll out Internet Protocol based systems, including PONs, CMTS, IP DSLAMs and ot ... read more |
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