| Design Constraint Verification and Validation: A New Paradigm by Cadence Design Systems, Inc. in EE Times EDA Designline |
June 18, 2007 -- Over the years, EDA tools have matured considerably. They now aid in design and verification of all aspects of chip manufacturing. One area that has lagged behind is the validation of design constraints. While chip design, funct ... read more |
| Massively Parallel Processors for DSP: Part 1 by Berkeley Design Technology, Inc. (BDTI) in EE Times Signal Processing DesignLine |
June 18, 2007 -- In the last few years a number of start-up companies have announced massively parallel processors for embedded DSP applications. With their arrays of processing elements, these processors target high-end digital video, software- ... read more |
| Data Compression Tutorial: Part 1 by EE Times Signal Processing DesignLine |
June 14, 2007 -- Data transmission and storage cost money. The more information being dealt with, the more it costs. In spite of this, most digital data are not stored in the most compact form. Rather, they are stored in whatever way makes them ... read more |
| The Incredible Journey of an 800-ps Period by Xilinx, Inc. in EE Times Programmable Logic Designline |
June 13, 2007 -- The size of one bit period at 1.25Gbps is 800ps, the data rate where even an interface with LVDS signaling probably cannot withstand all the sources of uncertainty in the journey from transmitter to receiver. Like the yellow-bri ... read more |
| Implementing FFTs on the MAXQ2000 Microcontroller by EE Times Signal Processing DesignLine |
June 13, 2007 -- Many of the latest 16-bit microcontrollers include hardware multiplication so that they can execute time-critical signal-processing algorithms, eliminating the need for a separate digital signal processor (DSP) chip in the syste ... read more |
| Next-Generation VoIP and the Role of DSP by Texas Instruments, Inc. (TI) in EE Times Signal Processing DesignLine |
June 11, 2007 -- The rapid growth of Voice over IP (VoIP) is pushing IP phone suppliers to add new capabilities and features while continually improving the quality of voice service. To meet these demands, IP phone designers need processors that ... read more |
| FFT Convolution and the Overlap-Add Method by EE Times Signal Processing DesignLine |
June 7, 2007 -- This article presents two important DSP techniques, the overlap-add method, and FFT convolution. The overlap-add method is used to break long signals into smaller segments for easier processing. FFT convolution uses the overlap-a ... read more |
| External Components Improve SAR-ADC Accuracy by Texas Instruments, Inc. (TI) in EDN Magazine |
June 7, 2007 -- It is tempting to use an op amp to directly drive the input of a SAR (successive-approximation-register) ADC. Unfortunately, this configuration can limit circuit performance. An external RC (resistor-capacitor) network better iso ... read more |
| Rise of Multiprocessing/ Multithreading Sharpens Focus on Interrupts by Express Logic, Inc. in Electronic Design Magazine |
June 7, 2007 -- Potentially substantial performance gains from the use of multithreading and multiprocessing architectures have captured the attention of designers of consumer devices and other electronic products. Multithreading uses cycles whe ... read more |
| Hop, Jump, and Spread: Wireless Machine-to-Machine Interfaces by EDN Magazine |
June 7, 2007 -- Wireless machine-to-machine interfaces represent the third wave of computers. The first wave was business computers, expensive mainframe and supercomputers affordable only to the largest businesses. This phase appeared and grew d ... read more |
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