| Using FPGAs to Interface with Digital Communication Protocols by National Instruments Corp. in EE Times Programmable Logic Designline |
June 6, 2007 -- Custom or proprietary digital protocols are commonly used in today's world for device or sub-system communication in everything from aerospace to consumer electronics. Many of these applications also use popular standards like SP ... read more |
| Practical Power Network Synthesis for Power-Gating Designs by Synopsys, Inc. in EE Times EDA Designline |
June 5, 2007 -- Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are ... read more |
| Achieving Certified IP Quality Efficiently by OneSpin Solutions GmbH in EE Times EDA Designline |
May 29, 2007 -- While the increasing use of design intellectual property (IP) has considerably reduced design effort per gate for the chip designer, it has had an inverse effect on the chip-level integration and functional verification effort. I ... read more |
| In the Eye of the DFM/DFY Storm by Pyxis Technology, Inc. in EE Times EDA Designline |
May 25, 2007 -- The phrase "eye of the storm" refers to the relatively calm center of a hurricane, where winds are light and the skies are only slightly cloudy, or even clear. If the eye of the hurricane passes over during the daytime, one might ... read more |
| Small, High-Performance ICs Require Wafer-Level RF Measurements by Cascade Microtech, Inc. in EDN Magazine |
May 24, 2007 -- Continuing increases in the speed of semiconductor devices combined with higher levels of integration, on-chip wireless functions, and the usage of mixed-signal-device designs are driving new requirements for wafer-level-RF measu ... read more |
| Taking a Bite Out of Power: Techniques for Low-Power ASIC Design by EDN Magazine |
May 24, 2007 -- Until recently, low-power digital IC design has been an area for specialist or guru IC designers. However, most IC design engineers will have to learn a variety of low-power-design techniques as ASICs and SOCs (systems on chips) ... read more |
| How to Simplify Hardware Prototyping with EXP Modules by Avnet Electronics Marketing in EE Times Programmable Logic Designline |
May 23, 2007 -- The new EXP expansion module specification defines a versatile, high performance, cost-effective way for FPGA designers to add functionality to their prototype platforms. By using EXP-enabled boards, designers can customize their ... read more |
| Measuring Scan Compression Performance by Synopsys, Inc. in EE Times EDA Designline |
May 21, 2007 -- Scan compression reduces the amount of data needed for digital IC manufacturing tests, thereby lowering the cost of executing patterns on the tester. EDA solutions for implementing scan compression on-chip are readily available, ... read more |
| Timing Constraints Generation Technology by Atrenta, Inc. in EE Times EDA Designline |
May 17, 2007 -- As design complexity has scaled upward, the need to provide accurate physical constraints like timing, area, power and port locations have become increasingly important. Of these, timing constraints are the most difficult to prov ... read more |
| Equivalent Results: A Methodology to Measure the Effects of High-Speed Compression by EE Times Programmable Logic Designline |
May 16, 2007 -- As analog-to-digital (A/D) and digital-to-analog (D/A) converter sample rates continue to rise, many DSP systems that use fixed-bandwidth network and storage elements from the PC world often fall behind, creating an opportunity f ... read more |
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