| Signal Integrity Analysis in Wireless SoCs by Coupling Wave Solutions (CWS) in EE Times EDA Designline |
May 14, 2007 -- The growing demand for cheap consumer wireless applications calls for unprecedented levels of integration. Huge digital IPs, such as microprocessors, digital signal processors, or encryption engines, are being assembled together ... read more |
| PCI Express Prompts Quiet Evolution by EDN Magazine |
May 10, 2007 -- Largely unknown to users, the PC industry, with
embedded computing following close behind, is in the middle of a quiet shift in
technology. The overtaxed PCI (Peripheral Component Interconnect) bus for add-in
cards is slowl ... read more |
| Extreme Low-Power Design by EDN Magazine |
May 10, 2007 -- Modern implantable medical devices, such as pacemakers and cardioverter defibrillators, use aggressive power-management techniques to reduce SOC power. A typical modern pacemaker may consume on average only a few microamperes of ... read more |
| Interface Overkill? Is eSATA Necessary for Your Next System Design? by EDN Magazine |
May 10, 2007 -- High-performance external storage is a godsend for consumers averse to cracking open their gear’s enclosure to upgrade its storage capacity or for manufacturers and service providers averse to having their customers tackle such s ... read more |
| Verifying Configurable Verification Interfaces Using OCP by Jasper Design Automation in EE Times EDA Designline |
May 10, 2007 -- The Open Core Protocol (OCP) is a synchronous socket interface specification that is widely used in the semiconductor industry today for system-on-chip (SOC) designs. The flexible nature of the implementation makes it widely appl ... read more |
| How to Choose an RTOS for Your FPGA and ASIC Designs by Zeidman Technologies, Inc. in EE Times Programmable Logic Designline |
May 9, 2007 -- This article examines different options for putting a real-time operating system (RTOS) on a system-on-hip (SOC). There are basically three options: purchase an off-the-shelf RTOS, write your own RTOS, or use a software synthesis ... read more |
| Analog and Mixed-Signal Connectivity IP at 65nm and Below by Synopsys, Inc. in EE Times EDA Designline |
May 7, 2007 -- The demand for connectivity intellectual property (IP) for high-speed serial buses such as USB 2.0, PCI Express, SATA, DDR2 and HDMI is increasing as these standard interfaces are included in SOCs designed for applications such as ... read more |
| A "How To" Tutorial on Logic Analyzer Basics for Digital Design by Agilent Technologies, Inc. in EE Times Programmable Logic Designline |
May 2, 2007 -- Let's assume that you need to simultaneously look at the inputs and outputs of a 16-bit counter to determine a timing error, but you have only a 2-channel scope – how do you look all of the required signals? Or let's suppose that ... read more |
| EDN 2007 DSP Directory by EDN Magazine |
April 30, 2007 -- The directory offers not only top-level descriptions of each company's DSP offerings, but also device tables and detailed pages dedicated to each company's devices, cores, development tools, and other products. These detail pag ... read more |
| How to Build Ultra-Fast Floating-Point FFTs in FPGAs by Andraka Consulting Group, Inc. in EE Times Signal Processing DesignLine |
April 30, 2007 -- Engineers targeting DSP to FPGAs have traditionally used fixed-point arithmetic, mainly because of the high cost associated with implementing floating-point arithmetic. That cost comes in the form of increased circuit complexit ... read more |
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