| Using Sub-RISC Processors in Next Generation Customizable Multi-Core Designs: Part 3 by EE Times Embedded |
April 24, 2007 -- With TIPI (Tiny Instruction-set Processors and Interconnect) PEs, we can create architectures that are good matches for the application's concurrency. Process-level, data-level, and datatype-level concurrency are all considered ... read more |
| Rigorous Automated Verification Yields High Quality Silicon by Texas Instruments, Inc. (TI) in EE Times EDA Designline |
April 24, 2007 -- Our passion to achieve high quality silicon led us down a new road when it came time for functional verification of a project larger than any previous ASIC in our team's history. In this paper we describe why our functional ver ... read more |
| Understand Packet-Processing Performance when Employing Multicore Processors by Intel Corp. in EE Times Embedded |
April 24, 2007 -- Many CPU manufacturers now deliver two cores per processor socket, with four cores on the way, and even more to follow. But harnessing multicore processor performance depends on the software developers' ability to make efficien ... read more |
| What's Different About Multiprocessor Software? Part 3 by EE Times Embedded |
April 23, 2007 -- An alternative approach to multiprocessor performance analysis is SymTA/S. It is based on events [Hen05]. The inputs and outputs to the system and between the processing elements are modeled as events. Unlike rate-monotonic ana ... read more |
| Real-Time Operating Systems for DSP: Part 1 by EE Times Signal Processing DesignLine |
April 19, 2007 -- Modern DSP applications must respond quickly to many external events, be able to prioritize processing, and perform many tasks at once. These complex applications are also changing rapidly over time, responding to ever changing ... read more |
| Capturing and Sharing Intellectual Property in PCB Design by Mentor Graphics Corp. in EE Times EDA Designline |
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April 19, 2007 -- This article discusses the disconnect between the
digital design engineer's vision of bus structures on the printed circuit board
(PCB) and the failure of tools to capture and route this vision in an efficient
manner. < ... read more |
| A Methodology for Front-End Ppower Predictability by Cadence Design Systems, Inc. in EDN Magazine |
April 18, 2007 -- Power closure has moved to the forefront of design challenges for today's chip projects. Leakage power increases with each new process generation. Smaller geometries enable more functionality to be fit into a smaller space, run ... read more |
| Using Sub-RISC Processors in Next Generation Customizable Multi-Core Designs: Part 2 by EE Times Embedded |
April 17, 2007 -- In Architecture Description Languages (ADLs) such as ISDL and nML, designers model an instruction set, and then a correct-by-construction synthesis tool generates a matching architecture and the appropriate software development ... read more |
| What's Different About Multiprocessor Software? Part 2, Multiprocessor Scheduling and Dealing with Tasks, Flows, Buffers and Data Dependencies by EE Times Embedded |
April 16, 2007 -- In general, multiprocessor scheduling is NP-complete. That is, if we want to minimize total execution time on an arbitrary processor, we have no known way to find the shortest schedule in polynomial time.
Of course, many N ... read more |
| EDN 2007 DSP Directory: The Best of Both Worlds by EDN Magazine |
April 12, 2007 -- The EDN 2007 DSP Directory again groups an
ever-expanding list of digital-signal-processing resources into a single
repository. The number of companies, devices, cores, and offerings in the
directory continues to e ... read more |
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