| SoCs Can Hold Key to System Security by MIPS Technologies, Inc. in EE Times Embedded |
April 2, 2007 -- SoC designers are increasingly aware of the need for security, in addition to performance, in consumer devices to protect both the device and its content from tampering and copying.
Designing a secure system requires a chip ... read more |
| Challenge the Assumptions on FPGAs by Xilinx, Inc. in EE Times Signal Processing DesignLine |
April 2, 2007 -- Today's high-performance, DSP-optimized FPGAs are already playing a key role in the world within which the DSP design community finds itself—a world of rapidly evolving and converging standards, critically short market windows, ... read more |
| Migrating FPGAs to Structured ASICs in Avionics to Reduce SEU Susceptibility by Altera Corp. in DSP-FPGA.com |
April 1, 2007 -- The use of FPGAs in many applications is rapidly increasing. With the attributes of reconfigurability and design-to-working part times much faster than those of ASICs, FPGAs offer avionics engineers advantages not available in m ... read more |
| Efficient Simulation and Validation for Mixed-Signal SOCs by EDN Magazine |
March 29,2007 -- The IC-design groups tackling complex digital-IC projects often have problems attaining complete system coverage of their designs. But when they add analog content into their designs, attaining coverage becomes a nightmare becau ... read more |
| Pragmatic Adoption of Formal Analysis by Cadence Design Systems, Inc. in EE Times EDA Designline |
March 29, 2007 -- Verification of today's system-on-chip (SoC) designs is a hard problem that keeps getting harder. Design size and complexity continually increase, while the market demands ever-tighter development schedules. Multiple approaches ... read more |
| How to Simplify the Process of Specifying Register-Maps and Auto-Generating Code and Other Deliverables by EE Times Programmable Logic Designline |
March 28, 2007 -- The register-map pattern is widespread in ASSP, ASIC, SoC and FPGA design. To narrow the scope of this article, we assume that you are developing an FPGA-based embedded system using Altera's SOPC Builder and NIOS II soft-proces ... read more |
| Using Sub-RISC Processors in Next Generation Customizable Multi-Core Designs: Part 1 by EE Times Embedded |
March 28, 2007 -- The now-common phrase "the processor is the NAND gate of the future" begs the questions: "What kind of processor?" and "How to program them?" When this is discussed, the focus is usually placed on RISC-based processors augmente ... read more |
| Putting FPGAs to Work in Software Radio Systems: Part 3 by Pentek, Inc. in EE Times RF & Microwave Designline |
March 28, 2007 -- Today's programmable logic technology offers significant advantages for designers who need to implement software radio functions. For designers looking to take advantage of an FPGA, the following examples of software radio syst ... read more |
| Signal Integrity Approaches Meet the Multi-Gbps Design Challenge by AWR Corp. in EE Times Planet Analog |
March 25, 2007 -- The wireless explosion has spawned a frontier with countless market opportunities for communications companies. The increasing complexity of today's electronics products, however, has created a myriad of issues for designing an ... read more |
| Model-Based Metal Fill Optimizes Planarization and Increases Yield by Synopsys, Inc. in EE Times EDA Designline |
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March 22, 2007 -- Copper interconnect was introduced to the mainstream at 130nm because of its
significant advantages compared to aluminum, such as reduction in resistivity
and power consumption and resistance to electromigration. Together ... read more |
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