| Improve Performance and Reduce Power Consumption in Mixed-Signal Designs by Peregrine Semiconductor Corp. in EE Times RF & Microwave Designline |
February 14, 2007 -- Designing high-reliability satellite communications systems is perhaps the most challenging mixed-signal design task. In addition to withstanding a wide range of temperatures and radiation, these systems also have to offer u ... read more |
| Achieving Completeness in IP Functional Verification by OneSpin Solutions GmbH in EE Times EDA Designline |
February 12, 2007 -- This article formalizes the concept of best possible verification quality — completeness — and describes a methodology, field-proven on many complex module and intellectual property (IP) designs, that tells you when verifica ... read more |
| How to Design an FPGA Architecture Tailored for Efficiency and Performance by Altera Corp. in EE Times Programmable Logic Designline |
February 12, 2007 -- Until relatively recently, the majority of FPGA architectures were developed using 4-input lookup tables (LUTs), where each LUT is constructed from SRAM bits storing digital (0 or 1) information. Also known as configuration ... read more |
| Designing Low-Power Multiprocessor Chips by LSI Corp. in EE Times Signal Processing DesignLine |
February 12, 2007 -- Just 10 years ago, the challenge chip designers faced was to design logic blocks with as few gates as possible to fit all the functions in a target die size. Today, advancements in semiconductor process technologies let desi ... read more |
| Generate FPGA Accelerators from C by EE Times Signal Processing DesignLine |
February 8, 2007 -- FPGAs are compelling platforms for hardware
acceleration of embedded systems. These devices, by virtue of their massively
parallel structures, provide embedded systems designers with new alternatives
for creating high-p ... read more |
| Getting the Most Out of ASIC Prototyping with FPGAs by Mentor Graphics Corp. in EE Times Programmable Logic Designline |
February 7, 2007 -- Over the past 18 months, there has been a growing adoption of the use of FPGAs to prototype ASICs as part of an ASIC verification methodology. With the development costs for ASICs skyrocketing – a typical 90nm ASIC/SoC design ... read more |
| Fixed vs. Floating Point: A Surprisingly Hard Choice by Analog Devices, Inc. (ADI) in EE Times Signal Processing DesignLine |
February 6, 2007 -- The advantages of floating-point processors are well known. Without a doubt, floating point implementations of many algorithms take fewer cycles to execute than fixed point code (assuming, of course, that the fixed-point code ... read more |
| Reducing FPGA Compile Time Using Parallel Compilation Methodology by Altera Corp. in EE Times EDA Designline |
February 5, 2007 -- Compile time for large designs has been a major bottleneck since FPGAs were first created. Reducing compile time offers a large benefit to users as their designs can be turned around quickly by analyzing and fixing failures a ... read more |
| Power Management: Analog Control vs. Digital by EE Times Power Management Designline |
February 5, 2007 -- To shed light on various aspects of the analog and digital control of power management, we'll clarify the fundamental differences between the technologies and determine how they affect system performance.
There is no ... read more |
| Designing Custom Embedded Multicore Processors by Altera Corp. in EE Times Embedded |
February 1, 2007 -- As embedded applications have proliferated, increasing performance demands have outstripped the ability of conventional single processors to provide effective solutions. The high clock speeds needed to achieve the necessary p ... read more |
|
