| Programmable Accelerators: Hardware Performance with Software Flexibility by CoWare, Inc. in EE Times Signal Processing DesignLine |
February 1, 2007 -- Higher product design costs and risks have been driving the electronics industry to an increased focus on developing "product platforms." The architecture often needs to be able to support new product requirements over the li ... read more |
| Weapons of Noise Detection by Electronic Design Magazine |
February 1, 2007 -- The war on noise now takes us into the next frontier: the high-speed serial backplane. Actually, this is about both noise and jitter, which is a practical approach, if not rigorously correct. Tektronix's Pavel Ziv ... read more |
| Maximizing EOS and ESD Immunity in High-Performance Serial Buses by Texas Instruments, Inc. (TI) in EDN Magazine |
February 1, 2007 -- EOS (electrical overstress) and ESD (electrostatic discharge) are the main causes of failures in semiconductors. Although EOS often takes the blame, ESD may sometimes accompany EOS. Did the assembly machinery zap the part? Di ... read more |
| Evaluating IP with the Four Cs: Compare, Consider, Collect, and Calculate by EDN Magazine |
February 1, 2007 -- There wasn’t a big ceremony with fireworks, a comedian, and showgirls in stunning dresses. There was no party, and there wasn’t even a press release, but, last year, the IP (intellectual-property) industry quietly celebrated ... read more |
| How to Architect, Design, Implement, and Verify Low-Power Digital ICs by Cadence Design Systems, Inc. in EE Times EDA Designline |
January 29, 2007 -- In recent years, power consumption has moved to
the forefront of digital integrated circuit (IC) development concerns. The
combination of higher clock speeds, greater functional integration, and smaller
process geometri ... read more |
| Programming Multi-Core DSPs by Cradle Technologies, Inc. in EE Times Signal Processing DesignLine |
January 29, 2007 -- Modern video-processing systems, like multichannel digital video recorders/analyzers used in security systems, run multiple applications such as image processing, compression and content analysis concurrently on many processo ... read more |
| How to Design 65-nm FPGA DDR2 Memory Interfaces for Signal Integrity by Xilinx, Inc. in EE Times Programmable Logic Designline |
January 24, 2007 -- This article presents practical techniques for incorporating "correctness by design" in DDR2 interfaces, from a signal integrity (SI) perspective, using the current generation of available design tools. Some common DDR2 desig ... read more |
| Test Data Provides Yield Improvement Metrics by EE Times EDA Designline |
January 22, 2007 -- Design for Yield (DFY) tools are expected to improve product yield. Design for Manufacturing (DFM) tools are expected to prevent yield loss. Speculation of the value of DFM or DFY technology can easily be delineated by simply ... read more |
| How to Achieve Software Load-Balance by Using a Message-Based Interconnect Protocol by EE Times Programmable Logic Designline |
January 22, 2007 -- The paradigm for using the PCI bus in a co-processor model in FPGA or ASIC implementations has been one of extending the core system's functionality through the addition of peripherals on the PCI bus. In a typical application ... read more |
| Converging Design Features in CPUs and GPUs by HPCwire |
January 19, 2007 -- As CPUs and graphics processors (GPUs) evolve, many of their design features are beginning to look remarkably similar, and as a result, many of today's most common workloads will soon have a choice about where to execute. Use ... read more |
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