| FPGA Floating Point Performance: A Pencil and Paper Evaluation by HPCwire |
January 12, 2007 -- HPC programmers are evaluating alternative accelerators to boost the performance of their applications. When looking at FPGAs, they are confronted with an array of new terminologies and concepts that can be difficult to under ... read more |
| Getting Serious About Transactional Memory by HPCwire |
January 12, 2007 -- The parallelization of computing, via multi-threading cores, multi-core processors and multi-processor systems is encouraging ever greater levels of application concurrency to take advantage of the proliferating CPUs. Multi-c ... read more |
| Video and Image Processing Design Using FPGAs by Altera Corp. in Video/Imaging DesignLine |
January 12, 2007 -- Innovations such as HDTV and digital cinema revolve around video and image processing and the rapid evolution of video technology. Major advances in image capture and display resolutions, advanced compression techniques, and ... read more |
| FPGAs vs. DSPs: A Look at the Unanswered Questions by Berkeley Design Technology, Inc. (BDTI) in EE Times Signal Processing DesignLine |
January 11, 2007 -- BDTI recently completed an in-depth analysis of FPGAs' suitability for DSP applications. We found that, in some high-performance signal processing applications, FPGAs have several significant advantages over high-end DSP proc ... read more |
| Why Multiprocessor DSP Systems Need CORBA by EE Times Signal Processing DesignLine |
January 9, 2007 -- Signal processing systems often include multiple
types of processors, such as digital signal processors (DSPs), general purpose
processors (GPPs), and field programmable gate arrays (FPGAs). These disparate
processors mu ... read more |
| Top 10 Methods for ASIC Power Minimization: Part 1 by Analog Devices, Inc. (ADI) in EE Times Power Management Designline |
January 8, 2007 -- The physical limits of CMOS technology scaling and the ever increasing number of on-chip features is causing low power design to move from being one of many design metrics to being the number one design metric. Some authors ha ... read more |
| C-based Design Methodology Accelerates ASIC/FPGA Design Cycles by CebaTech, Inc. in EE Times EDA Designline |
January 7, 2007 -- It's commonly understood that design cycles must continue to shrink due to market pressures, and that design verification is the biggest bottleneck in today's design cycle. Verification has become a nearly insurmountable obsta ... read more |
| Timing Is Everything in SOC Design by EDN Magazine |
January 4, 2007 -- It is a recurring nightmare. The SOC (system-on-chip) design has gone smoothly from day one. RTL (register-transfer level) for each block came in on schedule. Synthesis proceeded with hardly a glitch. Functional verification e ... read more |
| Optimize Your DSPs for Power and Performance by EE Times Signal Processing DesignLine |
January 4, 2007 -- The ever-growing demand for rich, multimedia signal processing in mobile devices raises a chronic technology challenge. The challenge is to squeeze higher functionality and performance within increasingly tighter power and spa ... read more |
| User-Friendly Model Simplifies Spice Op-amp Simulation by EDN Magazine |
January 4, 2007 -- Spice users can run into two types of problems with op-amp models: They need a model that is unavailable in their Spice library, or their library model may produce inaccurate simulation results for their application conditions ... read more |
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