| Interfacing FPGAs to DDR3 SDRAM memories by Altera Corp. in EDN Magazine |
November 8, 2007 -- DDR3 SDRAM memory architectures support higher bandwidths with bus rates of 600Mbps to 1.6Gbps (300 to 800MHz), 1.5-V operation for lower power, and higher densities of 2 Gbits on a 90-nm process. While this architecture is u ... read more |
| Traffic Management: A Growing Nightmare for SOC Designers by EDN Magazine |
November 8, 2007 -- The SOC (system on chip) began life in the image of the board-level computers that preceded it: as a central processor that a CPU bus connected to local memory and peripheral controllers. That CPU-centric, bus-oriented archit ... read more |
| Audio Coding: An Introduction to Data Compression - Part 3 by EE Times Audio Designline |
November 7, 2007 -- In MPEG Layer III coding the compression gain is mainly achieved through the unequal distribution of energy in the different frequency bands, the use of the psychoacoustic model, and Huffman coding. The unequal distribution o ... read more |
| Wireless Machine-to-Machine Networks by Digi International in EDN Magazine |
November 6, 2007 -- When designing monitoring or control devices that will communicate over wireless networks, there are currently two alternatives to consider: IEEE 802.11 a/b/g WLAN (Wireless Local Area Network) and ZigBee. Although they were ... read more |
| Do You Need a Reference Design and a Starter Kit? by Infineon Technologies AG in EDN Magazine |
November 5, 2007 -- As a hardware design engineer, there is a growing need to jump-start designs and evaluate the capabilities of potential suppliers quickly. However, the options available in the industry are growing rapidly and suppliers often ... read more |
| High Noon for FPGAs: Low-cost vs. high-end Showdown by EDN Magazine |
November 5, 2007 -- Although the market for high-end, high-priced SRAM-based FPGAs has matured into a gentlemanly duel between FPGA veterans Xilinx, Inc. and Altera Corp, the emerging low-cost-FPGA market has turned into the FPGA industry’s vers ... read more |
| Design with Verification: Not an Oxymoron by Cadence Design Systems, Inc. in EE Times EDA Designline |
November 5, 2007 -- Corporate efficiency consultants love to talk about "the dead moose on the table" — the important topic that everyone knows about but no one wants to bring up. In system-on-chip (SOC) verification, there is just such a dead m ... read more |
| Audio Coding: An Introduction to Data Compression - Part 2 by EE Times Audio Designline |
October 31, 2007 -- The Layer II coder provides a higher compression rate by making some relatively minor modifications to the Layer I coding scheme. These modifications include how the samples are grouped together, the representation of the sca ... read more |
| Optimizing GPS, Audio/Video Streaming Algorithm Designs with Atmel's Customizable CAP MCUs by Atmel Corp. in EE Times Embedded |
October 26, 2007 -- Various applications, ranging from GPS to audio/video stream processing, require complex algorithms to be executed in real time. Many of these algorithms follow industry standards that are upgraded periodically.
Engineers w ... read more |
| Improving CMRR in CAT-5 Video Links and Other Differential Video Transmitter-Receiver Applications by National Semiconductor Corp. in Video/Imaging DesignLine |
October 26, 2007 -- Operational amplifiers are extensively utilized in real-world video transmission applications where common-mode signals play an important role. One such application is in differential video transmitters-receivers over a CAT-5 ... read more |
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