| Common Multi-core Parallel Programming Problems and Their Solutions: Part 1 by Intel Corp. in EE Times Embedded |
October 26, 2007 -- Parallel programming has been around for decades, though before the advent of multi-core processors, it was an esoteric discipline. Numerous programmers have tripped over the common stumbling blocks by now. By recognizing the ... read more |
| ADCs for DSP: Part 4 by EE Times Signal Processing DesignLine |
October 25, 2007 -- Flash ADCs (sometimes called parallel ADCs) are the fastest type of ADC and use large numbers of comparators. An N-bit flash ADC consists of 2N resistors and 2N–1 comparators. Each comparator has a reference voltage that is 1 ... read more |
| EDN 2007 Microprocessor & Microcontroller Directory by EDN Magazine |
October 25, 2007 -- The 34th Annual Microprocessor & Microcontroller Directory presents a palette of processing options and development tools for your project. The directory contains a wealth of information on nearly 70 vendors and hundreds of p ... read more |
| Selecting Op Amps by EDN Magazine |
October 25, 2007 -- You would think that selecting operational amplifiers would be easy. After all, they have only three important pins: two inputs and one output. In designing a typical op amp, however, you must also consider the two power pins ... read more |
| Accellera VHDL Standard by SynthWorks Design, Inc. in EE Times EDA Designline |
October 25, 2007 -- In July 2006, the Accellera board approved a revision VHDL standard (revision 1076-2006-D3.0) put forward by the Accellera VHDL Technical Subcommittee (VHDL TSC). As an Accellera standard, revision 1076-2006-D3.0 is ready for ... read more |
| An Introduction to Audio Data Compression: Part 1 by EE Times Audio Designline |
October 24, 2007 -- Lossy compression schemes can be based on a source model, as in the case of speech compression, or a user or sink model, as is somewhat the case in image compression. In this chapter we look at audio compression approaches th ... read more |
| FPGA-Based Hardware Acceleration of C/C++ Based Applications: Part 4 by Nallatech, Ltd. in EE Times Programmable Logic Designline |
October 24, 2007 -- The aim of this article is to build on what Steve Casselman of DRC, Dan Poznanovic of SRC, and David Pellerin and his colleagues at Impulse C have already said. First, details will be given of Nallatech's hardware and softwar ... read more |
| The PoEP Standard and How to Get the Most from It by EE Times Power Management Designline |
October 23, 2007 -- A new standard now in development for power-over Ethernet, called Power-over-Ethernet Plus (PoEP), promises to extend the technology's potential by supporting much higher power levels. In this article, we take a peek at the c ... read more |
| Ensuring Power Designing Works at 65nm by TSMC (Taiwan Semiconductor Manufacturing Company) in EE Times EDA Designline |
October 22, 2007 -- When designers jump from the 90-nm to 65-nm process nodes, many factors conspire to make things more complicated. For instance, at 65nm, designers can fit a lot more functionality onto a chip, which draws considerably more po ... read more |
| RTL-ers Should Move to ESL by Calypto Design Systems, Inc. in eeDesign (EE Times EDA News) |
October 19, 2007 -- Fifteen years ago, designers were buzzing about a new design approach: Register Transfer Level (RTL) Design. There was a fundamental change underway in how chip designs were created and implemented. There were methodology exp ... read more |
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