| Sign-Off for Manufacturability by Cadence Design Systems, Inc. in EE Times EDA Designline |
October 8, 2007 -- The electronic design industry continues to push the limits of Moore's Law through smaller and smaller process nodes. As we reach 45nm, manufacturing and process control becomes increasingly difficult, making it imperative tha ... read more |
| 4G Wireless: Evolution or Watershed in SOC Architectures? by EDN Magazine |
October 4, 2007 -- The almost-mythological fourth generation of wireless service, 4G, could be the fountainhead of an entirely new way of thinking about SOC (system-on-chip) architectures. Or it could drive a simple evolution of today’s baseband ... read more |
| ADCs for DSP: Part 1 by EE Times Signal Processing DesignLine |
October 4, 2007 -- The trend in ADCs and DACs is toward higher speeds and higher resolutions at reduced power levels and supply voltages. Modern data converters generally operate on ±5 V (dual supply), 5 V or 3 V (single supply). In fact, the nu ... read more |
| How to Implement Double-Precision Floating-Point on FPGAs by Altera Corp. in EE Times Programmable Logic Designline |
October 3, 2007 -- An increasing number of applications in many vertical market segments, from financial analytics to military radar to various imaging applications, are relying on computations with floating-point (FP) numbers. These application ... read more |
| FPGA-Prototyping and ASIC-Conversion Considerations by AMI Semiconductor, Inc. (AMIS) in EDN Magazine |
October 3, 2007 -- The capacity and capability of modern FPGAs support the implementation of many digital systems, making FPGAs the platforms of choice for developing, prototyping, and deploying digital logic. Depending on the requirements of yo ... read more |
| Using FPGAs for Advanced Collision Avoidance Systems by Actel Corp. in EE Times Embedded |
October 3, 2007 -- Currently in development are several main collision-avoidance systems for passenger-car applications grouped into either passive or active safety systems. Passive systems include driver-assisted solutions such as backup or sid ... read more |
| Using Clock Margining for System Test Boundary Stability and Early Failure Prediction by Cypress Semiconductor Corp. in EE Times Embedded |
October 1, 2007 -- Overclocking techniques for clock margining utilizing programmable clock sources that help you determine the true system stability boundary conditions and system total timing budget (TTB) margin. If overclocking serves to push ... read more |
| Use an MCU's Low-Power Modes In Foreground/Background Systems by EE Times Embedded |
September 30, 2007 -- In today's world of battery-operated devices, the proper use of the low-power/sleep modes provided in most embedded microcontrollers (MCUs) is critical. At the same time, most high-volume MCU applications, such as home appl ... read more |
| Infrastructure DSPs for the Triple-Play Era by Texas Instruments, Inc. (TI) in EE Times Signal Processing DesignLine |
September 27, 2007 -- As multimedia content grows along with total traffic, equipment manufacturers are faced with unprecedented engineering challenges and opportunities. They must build a new generation of equipment that can handle a sharp and ... read more |
| Designing Small, Efficient AC/DC Switching Power Supplies by EDN Magazine |
September 27, 2007 -- AC/DC-power-supply design is evolutionary, rather than revolutionary, developing largely as a result of gradual improvements in semiconductors and passive-component technologies and materials. Invariably, power-supply-desig ... read more |
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