| Cost-Effective Two-Dimensional Rank-Order Filters on FPGAs by Xilinx, Inc. in EE Times Signal Processing DesignLine |
September 20, 2007 -- Rank-order filtering is a non-linear filtering technique in which an element is selected from an ordered list of samples. Two-dimensional (2D) filtering is performed on the contents of a rectangular window that slides acros ... read more |
| Multimedia Signal Processing with Programmable Logic by Altera Corp. in Video/Imaging DesignLine |
September 14, 2007 -- Multimedia devices or systems can range from a very basic consumer audio video player to a highly complex audio video capture, edit, and playback system used in a professional studio environment. Different types of technolo ... read more |
| Massively Parallel Processors for DSP: Part 2 by Berkeley Design Technology, Inc. (BDTI) in DSP Design, Ltd. |
September 13, 2007 -- The number of vendors offering massively parallel processors for digital signal processing is growing. As independent technology analysis company BDTI explained in its earlier article, there are a wide range of architectura ... read more |
| How Low Can You Go? A Look at 45-nm IC Design Challenges by EDN Magazine |
September 13, 2007 -- The 45-nm node promises SOC (system-on-chip) designers either a 40% increase in transistor counts over 65 nm or a 40% reduction in die size, but mask costs for 45-nm processes will run, at least initially, in the multimilli ... read more |
| How to Enhance Signal Integrity in High-Density FPGA-based Designs by Ittiam Systems, Ltd. in EE Times Embedded |
September 13, 2007 -- Platform verification boards typically have multiple FPGAs and hundreds of signals that are either terminated or non-terminated running between them. Checking the connectivity and locating fabrication and assembly faults be ... read more |
| How to Use FPGAs for Quadrature Encoder-based Motor Control Applications by Actel Corp. in EE Times Programmable Logic Designline |
September 11, 2007 -- Precisely tracking speed, acceleration, and position of a motor's rotor is an essential requirement for many motor control applications found in everyday equipment such as fax machines, elevators, and medical equipment. A c ... read more |
| Process Intelligent Modeling and Statistical STA improve DFM by Stratosphere Solutions, Inc. in EE Times EDA Designline |
September 11, 2007 -- It is no longer a mystery for designers and manufacturers of 45-nm chips that higher process variability negatively impacts design performance, predictability and parametric yield. Manufacturing and process variations resul ... read more |
| Top-down DSP Design for FPGAs by Mentor Graphics Corp. in EE Times Programmable Logic Designline |
September 9, 2007 -- Digital filtering of non-real-time signals has been performed for decades. The increased performance in today's silicon allows for these calculations to be accomplished in real-time, if the right hardware and algorithms are ... read more |
| Regression Test for OCP SystemC Channel Models by GreenSocs in EE Times EDA Designline |
September 4, 2007 -- In recent years the electronic system level (ESL) design methodology has been proposed to solve SoC design problems. SystemC, the main ESL hardware description language, is C++ based with hardware constructs such as modules, ... read more |
| TDR: Taking the Pulse of Signal Integrity by EDN Magazine |
September 3, 2007 -- Time-domain reflectometry will help you design and troubleshoot cables, connectors, fast PCB traces, and high-speed packages. With TDR instruments, you can ensure the signal integrity of fast digital signals as they travel a ... read more |
|
