Page loading . . .

  
 Category: Magazine & Journal Articles Online: Article Archive 2007: Thursday, June 20, 2013
Sort Entries by    
Use the input form on the right to search on a word or phrase.  
Page(s): 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (261 Entries)
TDR and S-parameter Measurements: How Much Performance Do You Need?  by Tektronix, Inc. in EDN Magazine

September 3, 2007 -- In computers, communications, and consumer electronics, the transition from parallel to high-speed serial-data transmission is creating new design challenges. Increasing data rates push more bits per unit time through the sa ... read more

The 802.11n Standard: Grown Up at Last  by EDN Magazine

September 3, 2007 -- Even for a wireless-communications standard, the 802.11n specification has over the last several years been subject to an exceptionally messy development process. Battling vendors and standards proposals, predraft and postdr ... read more

FPGA-based Design Yields Low-Cost Arbitrary-Frequency Generator  by EDN Magazine

September 3, 2007 -- An FPGA-based design is perfect for producing an arbitrary-frequency generator with broad applications in biomedical devices and anywhere else that you need signals of highly accurate, precisely known frequency. There are so ... read more

Enterprise Applications Go Embedded  by EDN Magazine

August 30, 2007 -- Embedded systems today reach far beyond their traditional "hidden" roles of controlling airplanes, industrial machines and military devices to situations such as medical examining rooms, delivery trucks and even the repairman' ... read more

Power-Sensitive 65-nm Designs Increase the Need for Transistor-Level Verification  by Synopsys, Inc. in EE Times EDA Designline

August 27, 2007 -- The vision expressed in Moore's Law; that the number of transistors on a chip would double approximately every two years, has been driving the semiconductor industry for many process generations. Most of us have probably commi ... read more

Speed MATLAB by Optimizing Memory Access  by MathWorks, Inc. in EE Times Signal Processing DesignLine

August 27, 2007 -- Most MATLAB users want their code to be fast, especially when it is processing very large data sets. Because memory performance has not increased at the same rate as CPU performance, code today is often "memory-bound," its ove ... read more

How to Support Multiple SD Devices Using CPLDs  by Xilinx, Inc. in EE Times Programmable Logic Designline

August 22, 2007 -- There has been an increasing demand to add multiple Secure Digital (SD) devices in a single system. The problem, however, is that most host devices/ processors, for example Intel PXA270, TI OMAP, or Qualcomm MSM processors, on ... read more

A Bluespec Hardware Implementation of Sudoku  by Bluespec, Inc. in EE Times EDA Designline

August 21, 2007 -- You might be asking, "Why would anyone create a hardware implementation of Sudoku?" Or even, "What does this have to do with me and what I do?" The simple answer is that we wanted a fun, thought-provoking demo. While this Sudo ... read more

Printed Electronics: Ink on the Brink  by EDN Magazine

August 16, 2007 -- Printed electronics may be the next big thing in our technological future and promises extremely low-cost, flexible, and disposable circuitry that you can manufacture with custom ink-jet printers or high-speed presses. Leading ... read more

Design For Manufacturing: Still not Ready for Prime Time?  by Electronic Design Magazine

August 16, 2007 -- In EDA, two primary areas still have room for innovation. One is at high levels of abstraction (above RTL), where a stalwart band of startups as well as one or two of EDA's heavier commercial hitters continue to seek a solid ... read more




 Search for:
            Site       Current Category  
   Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.579  0.5625