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 Category: Magazine & Journal Articles Online: Article Archive 2008: Friday, May 24, 2013
How to Achieve Design Flexibility for Free Using Structured ASIC Approaches  
Publication: EE Times Programmable Logic Designline
Contributor: ViASIC, Inc.
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March 26, 2008 -- Design readiness enables companies to respond quickly to design needs, but how can its true cost be determined? And which solutions, full custom ASIC, FPGA, or structured ASIC, are optimal for a given situation?

Although management and marketing often dictate that the engineering design department must be flexible and responsive, measuring the flexibility of a department is illusive at best. One way to start is by creating a valid metric for design response time, which can be used to help evaluate potential improvements and determine which ones are effective.

By Mark Goode. (Goode is president and CEO of ViASIC, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Programmable Logic Designline website.

Read more about
ViASIC, Inc.
on SOCcentral.com

Keywords: EE Times Programmable Logic Designline, ViASIC, structured ASICs, ASIC design,
580/25399 3/26/2008 5543 295


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