April 14, 2008 -- As processors bring ever higher levels of bandwidth on-chip, embedded ASIC and SoC designers have migrated to the PCI-Express (PCIe) interface to serve complex I/O demands. Representing one of the most successful standards in the history of electronics design, this widely used interface offers a high-speed, low-pin-count interconnect with a combination of performance, reliability and cost benefits.
Despite its widespread adoption in embedded applications, implementing a PCIe interface on chip is not a simple task. One of the first challenges designers face is selecting the right PHY IP. Dozens of companies offer PCIe PHYs. But they differ widely in quality and support capabilities.
The first step to take in this selection process is to ensure that the PHY IP you select complies with the latest version of the PCIe standard. Ask the vendor if the IP has achieved PCIe compliance in its intended manufacturing process and fab. It is also important to verify if the IP supports power level management.
By Wouter Suverkropp. (Suverkropp is with ChipX Corp.)
This brief introduction has been excerpted from the original copyrighted article.
