|Publication: EE Times EDA Designline|
November 3, 2008 -- With the advent of System-on-Chip technology, designs are becoming bigger in size and thus highly complex, time-to-market is becoming critical, and at the same time, RTL methodologies are generally becoming insufficient to fit into this new role. These factors are driving designers to explore new methodologies for early verification of complex IPs (HW as well as SW) as well as complete system. We at STMicroelectronics have set up a design flow that starts with highly abstracted, easier to write models to cycle accurate or RTL models of IP. While moving to lower levels of abstraction, the modeling becomes complex and so does the verification of the IP. Our approach is best suited to this scenario because it permits us to run same test benches/test scenarios in similar environments throughout, hence permitting the reuse of all the test cases and environments across the complete development cycle efficiently.
By D. Singh, N. Sharma, V. Upadhvava, A. Hazra, A. Jain, A. Goel, and R. Hakhoo. (Singh, Sharma, Upadhvava, Hazra, Jain, Goel, and Hakhoo are all with STMicroelectronics.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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|Keywords: EE Times EDA Designline, STMicroelectronics, SystemC, transaction level modeling, transaction-level modeling, TLM, ASICs, ASIC design, IP, intellectual property, cores, FPGA prototyping, EDA tools,|
|580/27297 11/3/2008 7319 427|