Page loading . . .

  
 Category: Magazine & Journal Articles Online: Article Archive 2008: Saturday, May 25, 2013
X Marks the Spot...the Intersection of Eco- and Financially-Friendly Computing  
Publication: EE Times Programmable Logic Designline
Contributor: XtremeData, Inc.
 Printer friendly
 E-Mail Item URL

November 12, 2008 -- FPGA companies have made a multi-billion dollar business by solving some of the toughest digital design problems in the industry. Radar, cryptography, WiMax/LTE, and software defined radio (SDR) are some of the markets where very large field-programmable gate arrays (FPGAs) have found homes in the past decade.

For many reasons, including cost pressure or stringent size, weight, and power (SWaP) requirements, these "constrained environments" have required extremely high-performance and high-efficiency architectures demanding the performance-per-watt advantages that FPGAs offer.

A key difference in electronic design between the last decade and the next will be the definition of "constrained environments." The applications I've mentioned so far have system and market demands that remove every last milliwatt of power, ounce of weight, or pennies of cost to deliver the optimal solution for that target market. Looking at the next ten years, let's explore if acceleration technology will help efficiently solve similar problems in other markets.

The world has already heard perhaps too much about "Green Computing," including low power and terms like "eco-friendly." This is only the beginning of a wave of requirements that will change server design for years to come. Linux clusters are great for scaling challenges and leveraging commodity components to solve large computer problems.

However, how "green" are they really? First, Linux clusters are built from x86 CPUs that typically only use some of their transistors for computation. The rest of those transistors are burning power and are not generating a solution. Clusters use tons of memory and mechanical storage that wastefully burns more power. Finally, the software running on these platforms typically can't take full advantage of multi-core CPUs, let alone tomorrow's "many-core" versions. The result is compounded inefficiency running on inefficiency.

It hit me recently in a conversation that there are more than a few markets left where efficiency hasn't been implemented and that are increasingly becoming "constrained environments." This intersection is where the next wave of application accelerators, such as FGPAs, will come into play.

By Geno Valente. (Valente is Vice President of Sales and Marketing for XtremeData, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Programmable Logic Designline website.

Read more about
XtremeData, Inc.
on SOCcentral.com

Keywords: EE Times Programmable Logic Designline, XtremeData, FPGAs, field programmable gate arrays, FPGA design,
580/27418 11/12/2008 4813 235


Designer's Mall
0.1914063



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.580  0.2304688