| How to Raise the RTL Abstraction Level and Design Conciseness with SystemVerilog: Part 2 by Mentor Graphics Corp. in EE Times Programmable Logic Designline |
May 14, 2008 -- With the advent of advanced HDLs, such as SystemVerilog, that provide new and powerful language constructs, current hardware modeling styles can now be enhanced both in terms of abstraction level and overall efficiency. Developin ... read more |
| High Availability in Embedded Systems: Always On by EDN Magazine |
May 13, 2008 -- As we approach the pervasive-computing era in which users will have round-the-clock access to information and services from any location, embedded-system designers are under growing pressure to boost the availability of servers, ... read more |
| Characterizing Nanometer CMOS PLLs, Sigma-Delta ADCs and AGCs by Silicon Laboratories, Inc. in EE Times EDA Designline |
May 13, 2008 -- A critical limitation in taping out high-performance mixed-signal ICs is the characterization of complex analog/RF blocks such as phase locked loops (PLLs) and analog-to-digital converters (ADCs). As we strive to extend our leade ... read more |
| Overcoming USB Measurement Test-Setup Issues by Cypress Semiconductor Corp. in EDN Magazine |
May 13, 2008 -- Measuring the signal quality of USB (Universal Serial Bus) interfaces requires that designers meet the stringent constraints of the USB-IF (USB Implementers Forum) specification. Nothing is more frustrating, however, than attempt ... read more |
| Host Bus Adapter (HBA) Verification by Breker Verification Systems, Inc. in EE Times EDA Designline |
May 6, 2008 -- Commercially available HVLs such as VERA, Specman and SystemVerilog have focused on capturing verification intent in terms of constraints for constrained random generators. In this approach, the constraint solver is used to random ... read more |
| 10-Gbit Ethernet in the Mainstream by EDN Magazine |
May 1, 2008 -- For several years, next-generation Ethernet capable of 10-Gbps speeds has been on the brink of entering the mainstream. Some areas of the network have for some time been using optical technology, and demand is increasing for 10-Gb ... read more |
| How to Raise the RTL Abstraction Level and Design Conciseness with SystemVerilog: Part 1 by Mentor Graphics Corp. in EE Times Programmable Logic Designline |
April 30, 2008 -- With the advent of advanced HDLs, such as SystemVerilog, that provide new and powerful language constructs, current hardware modeling styles can now be enhanced both in terms of abstraction level and overall efficiency.
D ... read more |
| Serial ATA and the Evolution in Data Storage Technology by Mentor Graphics Corp. in EE Times EDA Designline |
April 28, 2008 -- No question, storage devices and storage technologies have helped fuel our digital lifestyle. The amount of storable information and the requirement for fast, efficient, state-of-the-art storage technologies are the primary mec ... read more |
| Software Rules the Day in Multicore SoC Design by Electronic Design Magazine |
April 24, 2008 -- Looking back over the past 10 years or so, semiconductor process technology more or less kept pace with the demand for functionality in large-scale processor-based ICs. When the next-generation set-topbox IC needed more horsepo ... read more |
| What Floorplan Information Is Needed for Synthesis by Cadence Design Systems, Inc. in EE Times EDA Designline |
April 22, 2008 -- Modeling interconnect delay during synthesis has always presented a "chicken-and-egg" problem. Synthesis creates logic structures to meet timing goals, and interconnect is now a significant component of path delay, often exceed ... read more |
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