| SiPs Give More to Moore by Printed Circuit Design & Fab |
April 1 2008 -- SiP technology enables the efficient use of three dimensions through innovation in packaging and interconnect. The result supports continued increased functional density and decreased cost per function. Although there will be som ... read more |
| Open Verification Methodology: Why Now? by Cadence Design Systems, Inc. in EE Times EDA Designline |
April 1, 2008 -- Cadence and Mentor Graphics recently announced and shipped the Open Verification Methodology (OVM). This initiative focuses on providing a single, open, and interoperable SystemVerilog-based methodology and supporting class libr ... read more |
| Consider Your Materials Carefully in Microprocessor and ASIC Design by CPS Technologies in Electronic Design Magazine |
March 27, 2008 -- Microprocessor and ASIC designers must address the thermal and mechanical protection of IC die while considering system cost and reliability. Lids and heatsinks are common solutions for mechanical protection.
To ensure re ... read more |
| Implement a Complete ARV Controller in a Single SOC by Altera Corp. in Electronic Design Magazine |
March 27, 2008 -- From toys to mobile home appliances, there has been a proliferation of simple robotic vehicles, and they all rely on some form of a processor. Some use 8-bit microcontrollers, while others use custom silicon or combinations of ... read more |
| How to Achieve Design Flexibility for Free Using Structured ASIC Approaches by ViASIC, Inc. in EE Times Programmable Logic Designline |
March 26, 2008 -- Design readiness enables companies to respond quickly to design needs, but how can its true cost be determined? And which solutions, full custom ASIC, FPGA, or structured ASIC, are optimal for a given situation?
Although ... read more |
| EDN's 2008 DSP Directory by EDN Magazine |
March 24, 2008 -- Peel away the layers of complexity and find the perfect digital-signal processor for your project using our comprehensive listing of digital-signal-processing resources, including software-programmable processors, programmable ... read more |
| Statistical Timing Gets a Foothold in Leading-edge Designs by EDN Magazine |
March 24, 2008 -- Is statistical timing analysis really helping anyone, or is it an EDA-industry marketing ploy? This simmering debate within the leading edge of the chip design community bubbled to the surface in the plenary sessions Wednesday ... read more |
| Software-Defined Radio Platforms by imec in EE Times EDA Designline |
March 24, 2008 -- In the coming decade, SDRs will drive all types of wireless devices, answering the exploding demand for multi-standard, high-throughput wireless communication. Such SDRs will have rigorous constraints for energy consumption, re ... read more |
| Using IC Prototyping to Optimize Design Implementation by Synopsys, Inc. in EDN Magazine |
March 20, 2008 -- As IC-design size continues to escalate, time-to-market windows tighten, design requirements become more stringent, and device geometries shrink to nanometer proportions. Because of these constraints, employing prototyping earl ... read more |
| Digital TV for the Future: Hybrid Analog/Digital TV Receiver Design by Xceive, Inc. in EDN Magazine |
March 20, 2008 -- Analog is rapidly disappearing, but you still need to worry about developing analog-TV receivers because, in most parts of the world, it will be some time before manufacturers eliminate analog TVs. Even then, they may continue ... read more |
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