| Trip Points for IC Timing Analysis by Freescale Semiconductor, Inc. in EDN Magazine |
March 20, 2008 -- If you are a budding timing-analysis engineer or even a veteran, understanding trip points, which all major timing-analysis tools incorporate, is essential. Engineers use trip points in timing-analysis tools to calculate delay ... read more |
| How to Specify and Verify Power-Cycled SOCs for Checking and Coverage by Cadence Design Systems, Inc. in EDN Magazine |
March 18, 2008 -- Today's power-cycled SOC designs have power architectures that can be distressingly complex with multiple power domains that contain many power modes that require a thorough verification process.
The demand for more sophi ... read more |
| Multimode Sensor Processing Using Massively Parallel Processor Arrays by Ambric, Inc. in EE Times Programmable Logic Designline |
March 18, 2008 -- Multi-mode sensor processing – such as that for radar beamforming and for electro- optical (E-O) or infrared (IR) image processing – presents formidable computing problems. It requires extremely high data throughput and process ... read more |
| Design for Low-Power Manufacturing Test by Synopsys, Inc. in EE Times EDA Designline |
March 18, 2008 -- The very process of testing digital circuits routinely increases their dynamic power consumption to levels far exceeding their power specification. If the power consumption is great enough, it can result in failures at wafer pr ... read more |
| High Efficiency Challenges Power-Management Design by Electronic Design Magazine |
March 13, 2008 -- The semiconductor industry has always forced the power-supply industry to follow its trendsetting lead. For the last decade, that trend has been to cram more transistors into a single package, particularly microprocessors. This ... read more |
| Evolving Passive Optical Networks Demand FPGA Design Flexibility by Altera Corp. in EE Times Programmable Logic Designline |
March 12, 2008 -- FPGA technology, low cost optics, and a passive architecture have made significant contributions to passive optical networks (PONs) and to the evolution of these networks. System OEMs continue to discover that FPGAs deliver bot ... read more |
| Using FPGAs to Avoid Microprocessor Obsolescence by Lattice Semiconductor Corp. in EE Times Programmable Logic Designline |
March 3, 2008 -- One way that silicon suppliers reduce manufacturing costs is by discontinuing older product portfolios leading to microprocessor obsolescence. Multiple versions of those processor cores and a mix of integrated peripherals compli ... read more |
| Verify SOCs Faster and More Predictably with SystemVerilog and Constrained- Random Stimuli by Synopsys, Inc. in Electronic Design Magazine |
March 5, 2008 -- Verifying the integration and operation of new IP in a legacy system-on-a-chip (SOC) becomes challenging. This is true particularly when the legacy SoC environment was built using a directed test methodology and validation of ne ... read more |
| Low-Power Design for Analog/Mixed-Signal IP by Synopsys, Inc. in EE Times EDA Designline |
March 4, 2008 -- Power reduction and management techniques using multiple clock and power domains, dynamic voltage and frequency scaling and power gating are effective for digital circuits but for analog design, lowering power consumption must b ... read more |
| The Multicore Era Seeks a Parallel Paradigm by Electronic Design Magazine |
February 28, 2008 -- Parallel programming is hard. But debugging it is even harder. Unfortunately, taking advantage of multicore solutions like Intel’s 80-core TeraScale prototype will require some type of parallel-programming technique.
T ... read more |
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