| Software and RTOS Synthesis: The Next Step in Software Development? by Zeidman Technologies, Inc. in EE Times Programmable Logic Designline |
February 27, 2008 -- Just like Moore's Law has accurately predicted the growth of complexity of integrated circuits over the last 30 years or so, numerous studies have demonstrated exponential growth in embedded code size and complexity over the ... read more |
| Designing with QDRII+ and QDRII in One System by Cypress Semiconductor Corp. in EDN Magazine |
February 27, 2008 -- Memory devices are evolving to match the needs of applications that are in continuous demand, such as high-performance communications, networking, and DSP systems. Specialized memory products that optimize some architectures ... read more |
| Complex SOC Testing with a Core-Based DFT Strategy by Synopsys, Inc. in EE Times EDA Designline |
February 26, 2008 -- With scaling technology and increasing design sizes, power consumption during test and test data volume have grown dramatically — making it almost impossible to test an entire design once it reaches manufacturing. But using ... read more |
| VMM Application Packages: The Next Level of Productivity by Synopsys, Inc. in EDN Magazine |
February 21, 2008 -- The history of the EDA industry shows a clear, repetitive pattern. Designers develop new proprietary technologies, leveraging de facto and sanctioned industry standards; leading-edge users identify the most effective of thes ... read more |
| Analog's Answer to FPGA Opens Field to Masses by Electronic Engineering Times (EE Times) |
February 21, 2008 -- By making analog circuits easier to design and simulate, researchers at the Georgia Institute of Technology hope to further the cause of analog while enabling engineers to incorporate lower-power circuitry into their product ... read more |
| As SOCs Grow, Test-and-Measurement Instruments Move On-Chip by EDN Magazine |
February 21, 2008 -- It’s just geometry. As system-level ICs grow larger and more complex, they become impossible to observe and stimulate. Internal nodes aren’t accessible to bonding pads or even to probes. Signal voltages are small, noise thre ... read more |
| Comparing IP Integration Approaches for FPGA Implementation by Altera Corp. in EE Times Programmable Logic Designline |
February 20, 2008 -- Since the early days of computers and telephony, interconnection networks have been a critical part of electrical engineering. This has become even more critical in the era of VLSI circuitry because of the drive characterist ... read more |
| Multi-language Functional Verification Coverage for Multi-site Projects by Cadence Design Systems, Inc. in EE Times EDA Designline |
February 18, 2008 -- Today's design paradigm is changing rapidly, or to be more accurate, it has already dramatically changed! Time to market pressures imply that most of today's SOC designs are re-use based derivative designs. This paradigm shi ... read more |
| Power-Intent Standards Vie for Designers' Loyalties by Electronic Design Magazine |
February 14, 2008 -- About three years ago, timing closure for large system-on-a-chip (SOC) designs began to develop into one huge headache. Every EDA vendor’s toolset had its own interpretation of timing constraints, and there was little or no ... read more |
| Avoiding Pitfalls in Managing Embedded Systems Projects by Digi International in EDN Magazine |
February 12, 2008 -- Project Management has become so important across a multitude of disciplines that it has achieved the status of a discipline in and of itself. Some of the problems encountered in project management are common to any organiza ... read more |
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