| How to Manage Dynamic Power in a Microcontroller Using Its Non-Maskable Interrupt by Ittiam Systems, Ltd. in EE Times Programmable Logic Designline |
August 6, 2008 -- As portable systems become increasingly power-conscious, the need for smart power management becomes equally important. Besides the main processor, an auxiliary Microcontroller Unit (MCU) often resides on such systems to take c ... read more |
| Going from GDSII to OASIS by XYALIS in EE Times EDA Designline |
August 4, 2008 -- It's a banality to say that nowadays, databases for digital chips are more than huge. The physical description of an SOC, encoded in the classical GDSII format, now often goes over 20Gbytes. Files of up to 200Gbytes have been r ... read more |
| Virtualization for Embedded X86 Multiprocessor Applications by EE Times Embedded |
August 3, 2008 -- Virtualization of computer hardware has been used for many decades. The most widely noted early examples are those implemented by IBM on its mainframe hardware as a means to give its customers an easy upgrade from old "iron" to ... read more |
| How to Interface FPGAs to Microcontrollers by Atmel Corp. in EE Times Programmable Logic Designline |
July 30, 2008 -- As many as half of all embedded designs have an FPGA next to a microcontroller. The FPGA can be used to implement anything from glue logic, to custom IP, to accelerators for computationally intensive algorithms. By taking on som ... read more |
| Code Techniques for Processor Pipeline Optimization: Part 3 - Optimization for Control-oriented Operations by Intel Corp. in EE Times Embedded |
July 29, 2008 -- A typical application has a set of control-oriented operations, such as compare, branching, and looping. Certain applications, such as a data sort operation, are control heavy. Even in a more data-intensive application, such as ... read more |
| Code Techniques for Processor Pipeline Optimization: Part 2 - Optimization for Data Processing Operations by Intel Corp. in EE Times Embedded |
July 29, 2008 -- Data-processing operations are at the heart of any multimedia application. So expanding on the discussion in Part 1, what we will be concerned with here is the impact of the pipeline delay characteristics on the coding style in ... read more |
| Code Techniques for Processor Pipeline Optimization: Part 1 - Microarchitectural Optimization Philosophy by Intel Corp. in EE Times Embedded |
July 28, 2008 -- Optimization of a code segment can contribute greatly to its performance. An optimized application makes best use of all available microarchitectural features. In a pipelined processor, the key to optimization is to keep all the ... read more |
| Spread Spectrum Clock generators Reduce EMI and Signal Integrity Problems by EDN Magazine |
July 24, 2008 -- It is well-known that, during system development, critical signal-integrity and EMI (electromagnetic-interference) simulations are difficult, time-consuming, and error-prone due to their reliance on hard-to-predict models and pa ... read more |
| HDL-Design Challenges and Philosophies for Real-World ASIC Implementations by Silvus Technologies, Inc. in EDN Magazine |
July 24, 2008 -- New requirements for the MAC (medium-access control) and PHY (physical-layer interface) of a wireless-communications system can pose significant challenges for system designers looking to quickly get from development to producti ... read more |
| Shrinking ICs Need High Density in a Package Deal by Electronic Design Magazine |
July 24, 2008 -- The push is on for IC packages in smaller form factors, not only length- and width-wise, but also height-wise. Hence, the term "3D ICs."
Smaller form factors require greater density, and that means stacking chips and board ... read more |
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