January 28, 2009 -- Sundance Multiprocessor Technology. Ltd. and LogicDesign Solutions today announced the delivery of LogicDesign’s Serial ATA Host and Dual Host Controller IP for the Xilinx Virtex 5 FPGAs featured in the Sundance 7-Series of multiprocessing modules. The LogicDesign core is compliant with the Serial ATA II specification and supports signalling rates of 1.5Gbps SATA-Gen1 and scales to 3Gbps SATA-Gen2.

The 7-Series of multiprocessing modules from Sundance feature the fastest performing Virtex 5 FPGAs from Xilinx, C Series DSPs from Texas Instruments and are supported by an array of memory configurations, interconnect standards and design tools including 3L’s Diamond multiprocessor model and tool-suite, ISE from Xilinx and TI’s Code Composer Studio.

The availability of LogicDesign’s SATA IP on Sundance 7-Series hardware offers designers a multiprocessing development environment that features PCI-X, PCI-E, GigE, SATA and fibre optic modules for interconnect. In the form of a shrink wrapped SATA II compliant 3L Diamond multiprocessing task, LogicDesign is the first IP provider to offer SATA IP that is expressly designed for multiprocessing systems. Its 3L Diamond task is a self-contained block of code that incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. This offer enables quick and straight-forward integration of LogicDesign’s SATA IP into the multiprocessor system design.

The serial implementation of ATA is a high-speed serial replacement for the parallel implementation of ATA attachment of mass storage devices. Immediately available on Sundance hardware the LogicDesign Host and Dual Host Controller cores integrate the Transport layer, the Link layer and the PHY layer onto a single-chip, Virtex 5 FPGA solution. It is fully synchronous with system frequency at 37.5MHz for Gen-1 speed selection and 75MHz for Gen-2. The core implements shadow registers and SATA SuperSet registers, supports 8b/10b encoding and decoding and has state machine controlled power management (shared between PHY and Link layer). It features a 32-bit wide interface between the link layer and transport layer and a 128-word ingress/ egress FIFO between the transport and link layer.

Serge Sciberras, Managing Director at LogicDesign Solutions noted, "With our core competence in developing IP for FPGAs in embedded systems, the move to a multiprocessing partnership with Sundance was an obvious decision. By providing DO-254 documentation that supports the compliance of electronic hardware in airborne systems our SATA IP not only serves the video storage, and servers and storage markets, but also the aerospace and defense markets, and Sundance has established channels in all these segments."

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