Page loading . . .

  
 Category: News: News Archive 2009: Wednesday, June 19, 2013
Alvand Technologies Selects Berkeley Design Automation AFS Nano  
 Printer friendly
 E-Mail Item URL

April 9, 2009 -- Berkeley Design Automation, Inc. today announced that Alvand Technologies, Inc. has selected the company's Analog FastSpice Nano Spice simulator (AFS Nano) for analog and mixed-signal IP characterization.

"Alvand's high-performance, ultra-low-power analog and mixed-signal IP requires stringent and efficient characterization," said Mansour Keramat, President and CEO at Alvand Technologies. "AFS Nano provides us superior price/ performance for block-level design and verification. It consistently delivers true Spice accurate results up to 10X faster than traditional Spice on our ADC, DAC, and analog front-end designs."

Analog FastSpice is a unified circuit verification platform for analog, mixed-signal, and RF design. Always delivering true Spice accurate results, it provides 5 to 10X higher performance than traditional Spice, >1 million-element capacity, and comprehensive noise analysis. The AFS Platform is a single executable that uses advanced algorithms and numerical analysis to rapidly solve the full-circuit matrix and original device equations without any shortcuts. AFS Platform tools include: AFS Nano Spice simulator, Analog FastSpice circuit simulator, Noise Analysis Option device noise analyzer, and RF FastSpice multi-tone periodic analyzer.

Go to the Berkeley Design Automation, Inc. website to find additional information.

E-mail Berkeley Design Automation, Inc. for more information.

Read more about
Berkeley Design Automation, Inc.
and
Alvand Technologies, Inc.
on SOCcentral.com


Keywords: Berkeley Design Automation, Alvand Technologies, ASICs, ASIC design, analog design, mixed-signal design, IP, intellectual property, cores, circuit simulation, Spice, Spice-like, EDA tools,
589/28459 4/9/2009 917 115
Designer's Mall
4th Of July countdown banner
0.40625



 Search for:
            Site       Current Category  
   Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.589  0.453125