June 1, 2009 -- Evatronix SA, has announced the release of the 80186EC IP core, a 16-bit microprocessor compatible with the 80c186ec chip from Intel. The core implements a wide set of peripherals to address a variety of possible applications.

The C80186EC implements a DRAM refresh unit, three timers/ counters, two UARTs, four DMA engines, three 8-bit I/Os, two 8259-compatible components and a watchdog. Such a configuration makes it the most complex member of the Evatronix 80186 family.

For much smaller CPU overhead, the C80186EC can be complemented by the C80187 math coprocessor IP core from Evatronix, a component designed to aid floating point operations.

The C80186EC was developed with proprietary hardware modeling technology, the Personal Hardware Modeler. The PHM was employed for the functional reverse engineering that is usually required to overcome ambiguities of the original documentation and to implement undocumented features. It also enables the developed IP to be thoroughly checked against full original chip functionality covering all corner cases not only in RTL simulation but also in hardware supported co-simulation with utilization of an FPGA prototype.

The C80186EC has joined a broad line of other Evatronix IP cores equivalent to obsolete chips that cover the following processors: 8-bit Zilog Z80, 16-bit Motorola 68000, Intel 80187 numeric coprocessor as well as clones of the digital signal processors once manufactured by Texas Instruments (32025) and Motorola (56000). As all other Evatronix IP cores, these are also technology independent and can be implemented in any ASIC or FPGA designs.

Availability