June 1, 2009 -- Cadence Design Systems, Inc. today announced that the Chinese Academy of Sciences Institute of Computing Technology (ICT) has adopted the Cadence III System for accelerating the development of RTL design with a verification flow for its next-generation 64 million-plus gates Loongson III advanced multi-core microprocessor.

The deployment of the Incisive Xtreme III System for developing the ICT's advanced 65- and 45-nm multi-core processor enabled ICT engineers to accelerate system-level verification while validating software operations. The Xtreme III System supported the ICT's goals of accelerating hardware/ software development while reducing the risk of costly re-spins.

"The Xtreme III System has made a significant impact in accelerating our simulation runtime process by a factor of 860 times, and has made co-verification a predictable process for our next-generation Loongson III multi-core design," said Dr. Weiwu Hu, Chief Architect of the ICT's CPU division. "This Cadence technology has helped us improve overall productivity, predictability and quality of our Loongson III development."

Using Xtreme III, the ICT was able to accelerate simulation productivity and to find at least 10 critical system-level bugs that could only be exposed by running several billions of cycles in a system-level environment. The system enabled early access to a flexible, high-performance verification platform for hardware/ software co-development and delivered powerful built-in productivity features such as hot-swap and VCD-on-Demand. These capabilities enabled ICT developers to quickly bring up the system and find system-level bugs more simply than through traditional debugging methods.