June 25, 2009 -- Oasys Design Systems has taken the wraps off RealTime Designer, the first design tool for physical RTL synthesis of 100-million-gate designs, from RTL to placed gates in a single pass and in a fraction of the time compared to traditional synthesis. RealTime Designer features a unique RTL placement approach that eliminates unending design closure and iterations between synthesis and layout. RealTime Designer is in use in production flows at leading-edge semiconductor and systems companies worldwide.
"At Renesas Electronics Corp., RealTime Designer is used in both our customer ASIC flow, as well as for our own MCU designs," said Inoue Yoshio, Renesas Chief Engineer. "Predictable results and a convergent flow through layout are critical to get to market on time. Our conclusion is RealTime Designer produces better results than competitive tools and in a fraction of the time. This kind of performance is revolutionary. We are very impressed with the breakthrough technology from Oasys."
RealTime Designer follows a "Place First" methodology that takes RTL, partitions it into blocks, places the RTL in the context of a floorplan and implements each block all the way to placement. Chip-level constraints are automatically propagated across the blocks and the design is optimized for the best possible quality of results. During the optimization phase, RealTime Designer will repartition the design at the RTL and re-implement until the chip-level constraints are met.
Design teams must manually check for many results, such as design congestion, and send the design through synthesis. RealTime Designer is the first product to automate that process. Designers can give RealTime Designer the chip floorplan as input or, if no floorplan exists then Oasys will create a floorplan including macro, pin and I/O placement. At completion RealTime Designer produces a placed design and a netlist that meets the constraints in the context of the desired floorplan.
Synthesizing an entire TSMC 65nm design – 700k instances, 70 Macros, running at 600MHz, and a "golden" floorplan – RealTime Designer completed the task just 20 minutes and achieving design closure after a single iteration in place and route. In the traditional approach, the same design was synthesized after 14 hours, but it took 6 months of iterations to achieve the best result of 300ps wns.
Real Time Designer takes in standard inputs, including Verilog, standard timing and physical libraries, SDC timing constraints, and floorplan. VHDL will be available later this year. Output has been tested through all the popular place and route systems.
Go to the Oasys Design Systems website to find additional information.