July 27, 2009 -- Calypto Design Systems, Inc. has announced a fully automated design flow aimed at advancing the delivery of optimized, high-performance IP blocks found in SoC designs. Enabled by Calypto’s SLEC RTL tool and new analysis capabilities in itsPowerPro CG (clock gating) tool, Calypto’s Sequential Optimization Flow lets designers use a fully automated flow to optimize power, area, and timing for high-performance IP blocks, such as microprocessors and digital signal processors (DSPs). Using the flow, designers are also assured that functionality is maintained throughout the process.

"With each new generation of electronics products, SOC designers are challenged to deliver higher-performance functions that dissipate less power and occupy less silicon area than the previous generation," said Tom Sandoval, CEO of Calypto. "We have developed an automated flow that dramatically reduces the design time and resources required to deliver low-power, high-performance, differentiated functionality. As a result, even small SOC design teams are enabled to efficiently meet their strict power, performance and area goals using an automated method that includes proven tools for both optimization and comprehensive verification.”

Without an automated approach, design teams have been forced to engage in manual optimizations that can be costly, time consuming and error prone. This process frequently results in timing issues which, in turn, lead to increased circuit area and power consumption. Moreover, manual optimizations require extensive resources and unique skill sets, making the process off-limits to smaller design teams. Calypto’s new Sequential Optimization Flow addresses these challenges.

Calypto’s new Sequential Optimization Flow includes PowerPro CG, which takes an RTL design and automatically generates a power-optimized RTL design. Both the original and power-optimized RTL designs are run through a third-party synthesis tool, such as the Encounter RTL Compiler from Cadence Design Systems, Inc., to create two gate-level netlists. With the new automated analysis capabilities of PowerPro CG, the timing and power consumption of both netlists are automatically analyzed so that targeted retiming synthesis can be run on the power-optimized, gate-level netlist. Using Calypto’s SLEC RTL, functional equivalence between the original RTL and the new timing- and power-optimized gate level netlist is verified. By combining gate-level retiming with automated RTL power optimization and sequential logic equivalence checking, Calypto’s Sequential Optimization Flow enables SOC design teams to optimize power, area and timing for IP blocks and complex functions that were previously considered off-limits to such optimizations.

Calypto is showcasing the results of running the Sequential Optimization Flow on the Sun Microsystems OpenSPARC T1 processor core at the 2009 DAC. Sun has made this 64-bit, high-throughput, low-power core available to the public under the GNU v2.0 license. Calypto will demonstrate how running the core through the flow results in a 24 percent power advantage and almost five percent area advantage over the original core, with no performance impact. DAC attendees will see, firsthand, the effectiveness of the flow. Details of the Sequential Optimization Flow and the results of using the flow on the OpenSPARC core will be provided.

Availability and Pricing