| Arteris Enhances Network-on-Chip Offerings to Address Full Range of SOC Designs | | |
November 9, 2009 -- Arteris today announced the availability of two new on-chip interconnect products, the FlexNoC and FlexWay packages. With these offerings, Arteris expands the capabilities of its NoC solution to address the complete range of SOC design styles, sizes and complexities. The new technology builds on Arteris' technology for designing and implementing NoCs, and delivers an expanded, scalable capability to combine traditional bus-based interconnect approaches with its NoC technology. The solution also offers an enhanced tool set, called the FlexArtist tool suite, which further automates the process of designing on-chip interconnect at each stage of the SOC design flow.
The new product line addresses a broad array of interconnect issues facing IC designers today, including the design of ICs with lower power, higher performance and lower silicon area. One of the key innovations of the new offering is the ability to use its solution for both NoC and bus-type interconnect. This enables semiconductor makers to use FlexNoC and FlexWay IP for a broad range of complexity and performance requirements, as well as at various stages in the design process. .
The new Arteris product line adds two interconnect products:
- FlexNoC for implementing NoCs in medium to high-end SOC designs;
- FlexWay for addressing the needs of less complex SOC designs
|
The new Arteris IP products are supported by an enhanced design environment, the unified FlexArtist design tool set. The FlexArtist framework guides the design process starting from functional specification capture, through architectural refinement and ending with an automatic synthesis of a structural view used to drive the RTL to layout design flows. The FlexArtist system lets users output RTL and SystemC models to provide an interconnect model for every stage of the SOC design flow. The FlexArtist tool includes automatic interconnect verification and test bench generation features.
"The Arteris FlexNoC and FlexWay offerings expand the capabilities of NoC technology to implement an interconnect strategy that maps closely to the complexity of the ICs being designed. The interconnect solution scales with designers' needs and is managed from a unified tool set that provides enhanced automation and ease of use throughout the SOC design flow," said K. Charles Janac, President and CEO of Arteris.
New features for NoC and bus interconnect
- Low-latency architecture. The Arteris FlexNoC product gives users the choice, per connection, to use a standard packet format or a zero-latency packet format to carry protocol information. Such a choice lets the architect do the best trade-off between resource utilization and latency for simple designs and latency sensitive blocks or IP. The use of the zero latency packet format allows users to eliminate any penalty involved in the packetization process.
- Addressing the needs of simple SOC's. The Arteris FlexWay product can be used as a bus replacement for simple SOC designs. It can also be used to address peripheral interconnect applications on more complex designs. This product is geared toward conservation of wires and silicon area while using the same FlexArtist design tool set as other Arteris IP products.
- Scalability and a unified tool environment. Between the FlexNoC and FlexWay IP offerings, a semiconductor company can use Arteris technology for all of its SOC, FPGA and other projects. The new product line can be used from the most complex, large scale SOCs to relatively simple SOCs and FPGA designs.
- Structural Interconnect Synthesis. The FlexArtist tool set implements a new design flow and the capability to automatically synthesize a structural representation of an interconnect from an architectural description. The user still has the capabilities to manually control the synthesis process for fine performance tuning, and the FlexArtist tool offers an exceptional level of automation and productivity. Specification, architectural, structural and verification views are combined in a homogeneous framework. It supports AXITM, AHBTM, APBTM and OCP 2.2 IP communication protocols, enabling high levels of IP reuse.
|
Availability and Pricing
The FlexNoC and FlexWay products are available immediately. Pricing varies with project complexity and product features.
Go to the Arteris SA website to find additional information.
| E-mail Arteris SA for more information.
Read more about Arteris SA on SOCcentral.com |
| Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, on-chip interconnect, network-on-chip, NoC, Arteris,
| | 589/30050 11/9/2009 4035 146 | |
|
|
|
| | 0.375 |
|
|
| | |
|
|
Subscribe to SOCcentral's SOC Explorer Newsletter and receive news, article, whitepaper, and product updates bi-weekly.
|
|
|
Exec Viewpoint
The Many Faces of Low-Power Verification
 Ghislain Kaiser CEO, Docea Power
|
|
Exec Viewpoint
Maximizing the Value of Your Internal IP
 Warren Savage CEO, IPextreme
|
|
|
|
Barbara's Bytes
So, Just What Is ESL
 Barbara Tuck Senior Editor, SOCcentral
|
|
|
|
|
|
|
|
| Design Center |
| Whitepapers & App Notes |
|
|
|
|
|
| Live and Archived Webcasts |
|
|
|
|
|
| Newsletters |
|
|
|
|
|
|
About SOCcentral.com
Sponsorship/Advertising Information
|
|
|