November 23, 2009 -- Lattice Semiconductor Corp. and Praesum Communications, Inc. today announced the availability of the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3 FPGA family. According to Lattice, the core supports 1x, 2x and 4x lane configurations at up to 3.125-Gbps lane speeds, offering the lowest-cost, lowest-power programmable SRIO solution in the industry. Lattice also announced that it has licensed this IP core from Praesum and has full rights to use and sub-license the Serial RapidIO IP core.

RapidIO has won broad acceptance in wireless infrastructure applications, where it is used as a primary interconnect for DSP clusters in baseband processing. In the past, vendors had to rely on expensive, premium FPGAs for these applications. However, the combination of the Serial RapidIO 2.1 core and the LatticeECP3 FPGA will now let designers develop low-power infrastructure solutions for 3G, LTE and WiMAX without sacrificing performance or cost. The Serial RapidIO 2.1 core and other Lattice IP cores such as low-latency CPRI and GbE/SGMII comprise a comprehensive IP suite in support of wireless infrastructure applications.

About the Serial RapidIO 2.1 IP core

The core architecture for the Serial RapidIO 2.1 IP core includes the following features:

Allows for 1x, 2x, 4x lane configurations. Up to 3.125Gbps. Implements physical layer, transport layer, maintenance transaction handling and error management extensions. Provides infrastructure support for external logical layer functions, enabling maximum flexibility. Provides a choice of logical layer functions that are important for the application. Provides a choice of how logic layer functions interact with the rest of the system. Supports software implementations of control plane oriented functions such as doorbells and messages. Backward compatible with the v1.3 specification.

Availability and Pricing