Page loading . . .

  
 Category: News: News Archive 2009: Tuesday, May 21, 2013
Sort Entries by    
Use the input form on the right to search on a word or phrase.  
Page(s): 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 (1816 Entries)
Micrium Targets Memory Allocation in ARM Cortex-M3 Designs 

October 20, 2009 -- Micrium today announced the µC/OS-MPU, an enhancement of the company's flagship product, uC/OS-II. This add-on is designed to protect the uC/OS-II internal memory from task memory areas.

µC/OS-MPU introduces p ... read more

Agilent Technologies’ New Channel Simulator Mode Quickly Determines Ultralow Bit-Error Rate 

October 20, 2009 -- Agilent Technologies, Inc. today introduced a new statistical mode for its signal integrity Channel Simulator. The mode, offered as part of Agilent’s Advanced Design System (ADS) 2009 Update 1, is well-suited for desig ... read more

National Semiconductor Introduces Wireless Basestation IF Sampling Receiver Subsystem 

October 20, 2009 -- National Semiconductor Corp. has announced the availability of an intermediate frequency (IF) sampling receiver reference design for multi-carrier, multi-standard wireless basestations addressing standards. The subsys ... read more

Cadence and ARM Collaborate to Increase Engineer Productivity and Drive Down Time-to-Market for SOC Integration 

October 20, 2009> -- Cadence Design Systems, Inc. and ARM have entered into a strategic collaboration to create a next-generation SOC design flow that will accelerate time-to-market and lower the cost of SOC integration and verific ... read more

Intune Networks Selects Duolog's Bitwise Register Management Tool 

October 19, 2009 -- Duolog Technologies today announced that Intune Networks, a developer of optical networking equipment, has chosen Duolog's Bitwise tool to manage the register and memory-map infrastructures of Intune’s next-generation ... read more

Altera Secures Designs with Cyclone III LS FPGA Development Kit 

October 19, 2009 -- Altera Corp. has announced availability of the Cyclone III LS FPGA Development Kit. The kit features hardware and software solutions that let designers prototype and test designs for Altera's Cyclone III LS FPGAs, the ... read more

Austriamicrosystems Chooses ARM Cortex-M0 Processor for Mixed-Signal Applications 

October 19, 2009 -- ARM has announced that austriamicrosystems AG has licensed the ARM Cortex-M0 processor for future custom ASIC solutions. austriamicrosystems supplies ICs to a broad range of applications including automotive el ... read more

AWR Receives Three U.S. Government Small Business Innovation Research Program (SBIR) Grants 

October 19, 2009 -- AWR Corp. today announced that its Simulation Technology and Applied Research (STAAR) division, which develops Analyst 3D finite element method (FEM) software, has been awarded three grants for U.S. government-sponsore ... read more

Fujitsu Microelectronics Chooses Dolphin Integration's 100-dB Audio Codec IP 

October 19 2009 -- Dolphin Integration today announced that its 100-dB-proven audio codec CD10ACN50 has been licensed by Fujitsu Microelectronics Ltd. for integration into ICs to be manufactured in Fujitsu Microelectronics' 90-nm process ... read more

Lattice Simplifies System Control Applications with MachXO Control Development Kit 

October 19, 2009 -- Lattice Semiconductor Corp. today announced the immediate availability of the new MachXO Control Development Kit as well as 12 new reference designs, ideal for prototyping system control functions such as temperature a ... read more

SMIC Adopts Cadence DFM Solutions for 65- and 45-nm IP Library Development and Full Chip Production 

October 19, 2009 -- Cadence Design Systems, Inc. today announced that the Semiconductor Manufacturing International Corp. (SMIC) has adopted Cadence Litho Physical Analyzer and Cadence Litho Electrical Analyzer to more accurately ... read more

Xilinx and ARM Announce Development Collaboration  Featured

October 19, 2009 -- Xilinx, Inc. and ARM today announced a collaboration to enable ARM processor and interconnect technology on Xilinx FPGAs. Xilinx is adopting ARM Cortex processor IP, using performance-optimized ARM cell librarie ... read more

Tensilica Introduces Small, Ultra-Low-Power Dataplane Processor Core for Deeply Embedded Control 

October 19, 2009 -- Tensilica, Inc. today introduced the Xtensa 8 customizable processor, the eighth generation of its market leading low-power dataplane processor cores (DPUs). The Xtensa 8 processor core starts at a size of just 15,000 ... read more

STARC and Cadence Collaborate to Develop Next-Generation Analog/ Mixed-Signal Reference Flow 

October 19, 2009 -- Cadence Design Systems, Inc. announced today that it will collaborate with STARC to develop the Japanese electronic design consortium's next-generation analog/ mixed-signal reference flow. Cadence and STARC will ... read more

IAR Systems Launches Development Tools for ARM Cortex-R4 Processor 

October 19, 2009 -- IAR Systems AB has introduced comprehensive support for ARM Cortex-R4 processor in version 5.40 of IAR Embedded Workbench for ARM.

The package includes an editor, project management tools, a C and C++ compiler th ... read more

Three MosChip Devices Reach Volume Production with PLDA PCI Express IP 

October 19, 2009 -- PLDA announced today that MosChip Semiconductor Technology, Ltd. has successfully launched its MCS9990 PCI Express-to-USB2.0 host controller, incorporating PLDA's XpressRich2 PCI Express ASIC IP. MosChip used th ... read more

EMA Partners with Aldec to Provide Cadence OrCAD Users a Complete FPGA Design Solution 

October 14, 2009 -- EMA Design Automation, Inc. has partnered with Aldec, Inc. as an Authorized North American Distributor of Aldec Active-HDL. This partnership lets EMA deliver a comprehensive FPGA design environment to Cadence De ... read more

Siverge Networks Unveils Comprehensive Chip Solution for Mobile Backhauling Infrastructure 

October 14, 2009 -- Siverge Networks has announced a low-cost, high-performance, Wireless Universal Gateway chip solution for next-generation mobile backhauling infrastructures. The new offering, known as the SivGate, extends Siverge's G ... read more

Anchor Bay Achieves Silicon Success with Denali's DDR PHY Solution 

October 15, 2009 -- Denali Software, Inc. today announced that Anchor Bay Technologies, Inc., a leading supplier of video-processing semiconductors (ASICs) and systems, has successfully taped out its ABT2015 chip utilizing Denali's ... read more

Premier Farnell and Exar Sign Global Franchise Agreement 

October 15, 2009 -- Premier Farnell plc a leading multi-channel, high-service distributor supporting millions of engineers and purchasing professionals worldwide, has signed a new global franchise agreement with Exar Corp.

Under the ... read more




 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.589  3.5625