| Panasonic's AVC Networks Extends Deployment of SpringSoft's Verdi Debug System |
August 3, 2009 -- SpringSoft, Inc. today announced that AVC Networks Company of Panasonic Corp. has extended the terms of its comprehensive agreement for the SpringSoft Verdi Automated Debug System. The agreement with SpringSoft broadens ... read more |
| Nethra Uses Cadence Incisive Palladium to Speed Development of Advanced HD Image Processor |
August 3, 2009 -- Cadence Design Systems, Inc. today announced that Nethra Imaging, Inc. reduced the development time of a high-definition (HD) image processor design using the Cadence Incisive Palladium II Accelerator/ Emulator. P ... read more |
| Actel's Libero IDE v8.6 Targets Low-Power Design and Analysis |
August 3, 2009 -- Actel Corp. has just released Libero Integrated Design Environment (IDE) v8.6. The newest version of the Libero IDE offers designers several new features, including upgraded power analysis using the SmartPower tool and p ... read more |
| ispLEVER Design Tools Feature Updated CPLD Support and Faster, Modular Installation |
August 3, 2009 -- Lattice Semiconductor Corp. has announced the immediate availability of Version 1.3 of its ispLEVER Classic design tool suite which includes updated support for Lattice CPLDs (complex programmable logic devices), includi ... read more |
| Synfora Joins Synopsys System-Level Catalyst Program |
July 27, 2009 -- Synfora, Inc. has joined the Synopsys System-Level Catalyst Program, which is intended to accelerate the adoption of system-level design and verification tools and methodologies. In joining the program, Synfora wil ... read more |
| ARM, Chartered, IBM, Samsung, and Synopsys Collaborate to Deliver Vertically Optimized Solution for 32/ 28-nm Mobile SOC Designs |
July 27, 2009 -- In a move that addresses fundamental challenges in creating advanced system-on-chips (SOCs), ARM, Chartered Semiconductor Manufacturing, Ltd., IBM, Samsung Electronics, Co., Ltd., and Synopsys, Inc. today announced an agreement ... read more |
| Berkeley Design Automation Analog FastSpice Selected by NEC Electronics |
July 28, 2009 -- Berkeley Design Automation, Inc. today announced that NEC Electronics Corp. has selected the company's Analog FastSpice circuit simulator for complex-block characterization and full-circuit performance simulation of its a ... read more |
| Atrenta Announces Major Extensions to 1Team-Genesis Platform |
July 27, 2009 -- Atrenta, Inc. today announced major extensions to its 1Team-Genesis platform. 1Team-Genesis supports architectural level-chip assembly and provides a rich set of capabilities to plan the design, automate its assembly and ... read more |
| Freescale Achieves Design Cycle Reduction and Superior Silicon Predictability with Cadence Model-Based Physical and Electrical DFM Solutions |
July 28, 2009 -- Cadence Design Systems, Inc. today announced that Freescale Semiconductor has successfully taped out a 45-nm networking design using the Cadence "correct-by-design" prevention, analysis, implementation and signoff solutio ... read more |
| Anova's Variation Analysis Software Included in TSMC Reference Flow 10.0 |
July 27, 2009 -- Anova Solutions, Inc. haw announced that its path-based transistor-level statistic timing and power-analysis software ChronoVA PA has been included in TSMC Reference Flow 10.0. The software uses Stochastic Analysis Proces ... read more |
| Open SystemC Initiative Unveils Technical Working Group Milestones at DAC |
July 27, 2009 -- The Open SystemC Initiative (OSCI) today announced significant milestones that have been achieved by three of its working groups: the Transaction-level Modeling Working Group (TLM WG), the Synthesis WG and the Analog/ Mix ... read more |
| STMicroelectronics Adopts Cadence Encounter Signoff Solutions for Designs from 65 to 32nm |
July 27, 2009 -- Cadence Design Systems, Inc. today announced that STMicroelectronics, has adopted the complete Cadence integrated signoff solutions consisting of QRC Extraction and Encounter Timing System, for 65- and 45-nm design, and i ... read more |
| Tuscany Design Automation Introduces Web-Enabled Visualization of Complete IC Design Data |
July 27, 2009 -- Tuscany Design Automation, Inc. today introduced the Tuscany Dashboard, the first web-enabled solution for the visualization and control of IC design data, bridging front-end and back-end teams.
Design teams need "g ... read more |
| VeriSilicon Delivers Chip Designs on Time and at Lower Cost with Cadence InCyte Chip Estimator |
July 27, 2009 -- Cadence Design Systems, Inc. announced today that VeriSilicon has adopted the Cadence InCyte Chip Estimator to help predict area, timing, power and cost requirements earlier in the design process, allowing design teams to ... read more |
| Virage Logic Extends IP Technology to the 32/ 28-nm Processes |
July 28, 2009 -- Virage Logic Corp. has extended its advanced IP technology to the 32/28-nm process node with the tape out of a product test chip with multiple IPs optimized for a high-performance application for an early adopter customer ... read more |
| Cadence Achieves First-Silicon Results on 32-nm Common Platform Technology |
July 29, 2009 -- Cadence Design Systems, Inc. today announced first-silicon results on 32-nm Common Platform high-k metal-gate (HKMG) technology, manufactured at IBM. Cadence and the Common Platform alliance, comprising IBM, Chartered Sem ... read more |
| HDL Design House Announces Serial Rapid IO Soft IP Core |
July 31, 2009 -- HDL Design House (HDL DH) has announced the Serial RapidIO soft IP core (HIP 3300) compliant with RapidIO specification version 2.0.1 . HIP 3300 Serial RapidIO endpoint soft IP core is based on a generic, highly modular a ... read more |
| Arasan Chip Systems Announces e-MMC 4.4 Card Controller IP Core |
July 29, 2009 -- Arasan Chip Systems, Inc. has announced the availability of the Embedded MultiMedia 4.4 card controller IP compliant with the recently ratified JEDEC e-MMC 4.4 standard. Arasan's e-MMC 4.4 card controller lets memory card ... read more |
| Taiwan's ITRI Adopts Cadence C-to-Silicon Compiler to Boost Designer Productivity |
July 29, 2009 -- Cadence Design Systems, Inc. today announced that the Industrial Technology Research Institute (ITRI), a non-profit organization that serves to strengthen the technological competitiveness of Taiwan, has adopted Cadence C ... read more |
| Mentor Graphics Announces Linux and Nucleus Multi-OS Support for Marvell Sheeva Embedded Processors |
July 30, 2009 -- Mentor Graphics Corp. today announced the availability of a combined open-source Linux and Nucleus operating system (OS) solution for the Marvell Sheeva MV78200 dual-core embedded processor.
This dual operating syst ... read more |
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