| Synopsys' New DesignWare IP Slashes Power in Datapath Circuits |
July 20, 2009 -- Synopsys, Inc. today announced the DesignWare minPower Components, a new IP product that is an integral part of the Synopsys Eclypse Low Power Solution. The DesignWare minPower Components dramatically reduce power in data ... read more |
| Silicon Clocks Tapes Out Two Chips Using Ciranova PyCells |
July 20, 2009 -- Ciranova, Inc. announced today that Silicon Clocks, Inc. had successfully taped out two MEMS chips, implementing the company’s modular CMEMS (Standard CMOS + MEMS) process technology platform, using a process desig ... read more |
| Real Intent Announces New Functional Verification Solution to Ensure X-Robust Designs |
July 20, 2009 -- Real Intent, Inc.'s Ascent early functional verification product family now includes the first commercially available automated solution to ensure X-robust designs, available through the Ascent Path-Based Verification (PB ... read more |
| Microchip Technology Unveils New Family of Low-Power 8-bit PIC Microcontrollers with nanoWatt XLP Technology |
July 20, 2009 -- Microchip Technology, Inc. has announced a new family of 8-bit PIC microcontrollers (MCUs) featuring nanoWatt XLP technology, which enables extremely low sleep currents. The high-performance, low-power PIC18F13K22, PIC18 ... read more |
| Mentor Graphics Signs Trident Techlabs as New Distributor in India |
July 20, 2009 -- Mentor Graphics Corp. has signed Trident Techlabs Pvt., Ltd, previously a reseller of Altium’s products, as a distributor in India. Trident will offer Mentor’s PCB and ASIC/ FPGA products for systems design: Expedition En ... read more |
| Blue Pearl Software Announces Cobalt Timing Constraint Management |
July 20, 2009 -- Blue Pearl Software, Inc. has announced its Cobalt Timing Constraint Management product to help design engineers implement new designs more efficiently by automatically managing their complex timing constraint files for s ... read more |
| Achronix Deploys Synopsys IC Validator and IC Compiler for Next-Generation FPGA Design |
July 20, 2009 -- Achronix Semiconductor Corp. has deployed Synopsys, Inc.'s IC Compiler and the recently announced IC Validator, the newest addition to the Galaxy Implementation Platform, for designing its next generation of high-e ... read more |
| Sagantec Speeds Porting of High-Performance Interface IP at MoSys |
July 20, 2009 - Sagantec, Inc. recently announced that MoSys, Inc. has deployed Sagantec's Anaconda-M solution as part of it's methodology for automating and accelerating its process-porting flow. The Anaconda-M solution was succes ... read more |
| Siemens Uses Cofluent Design to Create Models for Virtual Platform Simulation |
July 20, 2009 -- CoFluent Design today announced that Siemens runs SystemC models created with CoFluent Studio on the CoWare Platform Architect SystemC kernel.
"Siemens uses CoFluent Studio to create timed transactional models of it ... read more |
| Cofluent Design Closes Modeling Gap for Virtual Platforms |
July 20, 2009 -- CoFluent Design's CoFluent Studio now allows the creation and automatic generation of SystemC models for CoWare Platform Architect and Synopsys Innovator products. Models can be integrated to virtual platform environments ... read more |
| Ramtron Extends V-Family Product Line with Serial 256-kbit F-RAM |
July 15, 2009 -- Ramtron International Corp. today announced two new serial nonvolatile F-RAM products that offer high-speed read/ write performance, low-voltage operation, and optional device features.
The 256-kbit devices, which ... read more |
| Ricoh Joins Power Forward Initiative |
July 15, 2009 -- Cadence Design Systems, Inc. announced today that Ricoh Co., Ltd. has joined the Power Forward Initiative after completing two complex power management system-on-chip (SOC) designs using the Cadence Low-Power Solution. As ... read more |
| NetLogic Microsystems and TSMC Collaborate on 40-nm Technology for Next-Generation Processors and 10/40/100 Gigabit Physical Layer Solutions |
July 15, 2009 -- NetLogic Microsystems, Inc. and TSMC (Taiwan Semiconductor Manufacturing Company) today announced their collaboration on the 40nm-G semiconductor process technology for NetLogic Microsystems’ next-generation advanc ... read more |
| Magma Announces Talus-Based RTL-to-GDSII Low-Power Reference Flow for UMC's 40-nm Process |
July 15, 2009 -- Magma Design Automation, Inc. has announced the availability of an integrated low-power IC implementation reference flow for UMC's advanced 40-nm process. This reference flow supports the UMC 40-nm process and the UMC 40- ... read more |
| EdXact and Altos Partner to Improve IP Characterization Throughput |
July 15, 2009 -- Altos Design Automation, Inc. and EdXact are partnering to further improve characterization turn-around time especially for large cells and macro blocks.
Through the Altos Pal O’Altos partnership program, th ... read more |
| CSR Deploys Altos's Liberate LV for Library Validation |
July 15, 2009 -- Altos Design Automation, Inc. today announced that CSR has adopted the Altos Liberate LV solution for library qualification and validation. Liberate LV has enabled CSR to ensure timing validation of its 90-nm standard cel ... read more |
| Cadence Introduces TLM-Driven Design and Verification Solution |
July 15, 2009 -- Cadence Design Systems, Inc. has introduced a unified TLM-driven design and verification solution and methodology enabling SOC designers to reap the benefits of transaction-level modeling (TLM). The Cadence solution combi ... read more |
| National Semi Adopts Cadence Virtuoso Simulation Solution for Complex Analog Designs |
July 15, 2009 -- Cadence Design Systems, Inc. announced today that National Semiconductor, Inc. has adopted the Cadence Virtuoso Accelerated Parallel Simulator to verify its large, complex analog designs. Verification engineers throughout ... read more |
| Altos Announces Liberate LV Library Validation Solution |
July 15, 2009 -- Altos Design Automation, Inc. today announced Liberate LV, an independent and comprehensive solution to validate cell libraries. Using Liberate LV, library teams will be able to assure the quality of all the electrical vi ... read more |
| Altos Releases Liberate MX for Highly Efficient Memory/ Macro Block Characterization |
July 15, 2009 -- Altos Design Automation, Inc. today announced Liberate MX, an ultra-fast, general-purpose library characterizer for memories and custom macro blocks. The new tool generates instance specific library models in Liberty form ... read more |
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