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 Category: Magazine & Journal Articles Online: Article Archive 2009: Thursday, May 23, 2013
High-Speed Board-Layout Challenges in FPGA/SDI Sub-Systems  
Publication: EE Times Programmable Logic Designline
Contributor: National Semiconductor Corp.
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November 18, 2009 -- Television and cinema have entered the digital age. Video pictures are used to transport at standard definition rate (270 Mb/s), upgraded to high definition rate (1.485Gbps), and are now migrating to 3Gbps. The migration to higher speeds enables higher resolution images for entertainment, but it also presents challenges to hardware engineers and physical layout designers. Many video systems are implemented with feature-rich FPGA and multi-rate SDI integrated circuits that support high performance professional video transport over long distances. FPGAs demand high density routing with fine trace width while high-speed analog SDI routing demands impedance matching and signal fidelity.

This article outlines the layout challenges facing hardware engineers and provides recommendations for dealing with these challenges.

By Tsun-Kit Chin. (Chin is with National Semiconductor Corp.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Programmable Logic Designline website.

Read more about
National Semiconductor Corp.
on SOCcentral.com

Keywords: FPGAs, field programmable gate arrays, FPGA design, PCB design, PCB layout, EE Times Programmable Logic Designline, National Semiconductor,
590/30170 11/18/2009 2228 213


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