| Programmable Chips: Piecing Together an Analog Solution by EDN Magazine |
July 23, 2009 -- Configurable analog ICs have been available in various forms for years, seemingly making less of an impression on the market than their digital cousins, FPGAs (field-programmable gate arrays). The current economic situation sudd ... read more |
| Optimizing Reliability and Power Efficiency In Embedded Wireless Systems by Cypress Semiconductor Corp. in EDN Magazine |
July 23, 2009 -- The use of wireless technology in embedded-system applications, such as industrial monitoring and control, home automation, remote control, and medical equipment, continues to grow rapidly, and the number of new applications tha ... read more |
| Medical Devices Get a Prescription for Wafer-Level Chip-Scale Packaging by Analog Devices, Inc. (ADI) in Electronic Design Magazine |
July 23, 2009 -- Portable health appliances and services are becoming ubiquitous. Constantly on, they must be efficient and "invisible." This brings new challenges regarding low power consumption and small size. Waferlevel chip-scale packages (W ... read more |
| High-Density IC Packaging Looks at the Third Dimension by Tessera Technologies, Inc. in Electronic Design Magazine |
July 23, 2009 -- Much has been written in the past few months about the upcoming sunset of Moore’s Law. Stated succinctly, Gordon Moore predicted in 1965 that the number of transistors in ICs would double every 12 months1. There have been other ... read more |
| Formal Methodology Validates Cache-Coherence Protocol by Jasper Design Automation in Electronic Design Magazine |
July 23, 2009 -- Bugs in RTL code are problematic, but a bug in an architectural specification can be catastrophic. If the bug remains undetected until post-silicon debugging, the design process essentially starts all over again. Thus, it’s cruc ... read more |
| Deinterlacing with FPGAs for HDTVs by Altera Corp. in Video/Imaging DesignLine |
July 15, 2009 -- Deinterlacing is a video processing function that is required to address legacy problems stemming from the generation of interlaced video that was widely used by the old analog CRT televisions.
An interlaced video is a suc ... read more |
| Versatile OTP Can Replace Several Memories by Sidense Corp. in Chip Estimate Corp. |
July 15, 2009 -- With the proliferation of embedded memory on all kinds of systems-on-silicon, designers are faced with a dilemma - how to select the right memory for each storage application on their chips. Even within the subset of non-volatil ... read more |
| Unleash the Power of Formal Technology for CDC Verification by Real Intent, Inc. in Electronic Engineering Times (EE Times) |
July 13, 2009 -- Clock domain crossing (CDC) verification has become a critical component in ensuring correct design operations for complex SOC. CDC verification is not a nice-to-have checklist item any more for ASIC and FPGA design and verifica ... read more |
| Barriers to Widescale Acceptance of Assertion-based Verification by Zocalo Tech, Inc. in Electronic Engineering Times (EE Times) |
July 13, 2009 -- Assertions serve as executable specifications describing the required and forbidden behavior of the design. The assertions are checked in every simulation run by binding assertion checkers/monitors to the design code. Assertion- ... read more |
| Parasitic Extraction: 3D or Not 3D, That Is the Question by Silicon Frontline Technology, Inc. in Electronic Engineering Times (EE Times) |
July 13, 2009 -- The design, verification and tapeout are complete, time to celebrate, to enjoy another successful design. At least until the silicon comes back. And then ...
If you are like most design teams at an advanced process node, t ... read more |
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