| A Platform for Performance Validation of Memory Controllers by NXP Semiconductors in Design & Reuse |
February 2, 2009 -- With growing gap between processor and memory speeds, the memory bandwidth has become performance bottleneck for media applications. The memory controller designs are getting optimized to reduce the latencies added by them. I ... read more |
| Advanced DRAMs Drive High-AR Etch Advances by Semiconductor International |
February 1, 2009 -- DRAM device manufacturers working to improve memory density and performance by shrinking design rules and die sizes face many challenges. Methods such as larger capacitor surface areas, higher dielectric constants and smaller ... read more |
| E-Beam Technology Breaks Through Complex Design Cycles by Semiconductor International |
February 1, 2009 -- Rapidly rising costs and increasingly complex design cycles for advanced standard cell and system-on-chip (SOC) devices have forced many potential foundry customers into postponing or canceling projects. Often, they make the ... read more |
| Trailblazing SuperSpeed USB Design and Verification by Electronic Design Magazine |
January 29, 2009 -- The eagerly awaited revision 3.0 of the Universal Serial Bus (USB) specification offers 10 times the speed of USB 2.0 even as it maintains backward compatibility with USB 2.0 and USB 1.1 devices. Early adopters ramping up the ... read more |
| Take the FPGA Plunge by Electronic Design Magazine |
January 29, 2009 -- FPGAs are expensive... and hard to use... and too slow... and difficult to program... and hard to debug... and they draw too much power... and require register-transfer-level (RTL) wizards. That’s the conventional developer w ... read more |
| Programmable Logic Innovation Is Overdue by Cswitch Corp. in EE Times Programmable Logic Designline |
January 27, 2009 -- The programmable logic industry has remained stubbornly resistant to change over the past 20 years of its existence. If you follow this industry, you know that the FPGA logic fabric that is implemented in the latest offerings ... read more |
| Identifying IP cores to Protect Your Investment by Design & Reuse |
January 26, 2009 -- IP core providers are increasingly aware of the need to protect their investment from either unintended or unlicensed usage of their IP core blocks. This would require identification of IP core blocks from any SoC. IP core id ... read more |
| How SLEC Improves Functional Verification by Calypto Design Systems, Inc. in EE Times EDA Designline |
January 23, 2009 -- Design teams commonly use system models for verification. System models have many advantages over register transfer level (RTL) code for verification, notably, because of their ease of development and runtime performance. The ... read more |
| Modern ADCs Improve CMOS Image Sensors by Chipworks, Inc. in EDN Magazine |
January 22, 2009 -- The last two years have seen many important developments in CMOS image sensors using a variety of architectures that employ different methods to achieve similar goals. The ADCs that the image sensors employ are keys to these ... read more |
| Simulation Gets Speed, Capacity Boost by EDN Magazine |
January 22, 2009 -- Speed, accuracy, and ease of use are key demands of designers employing simulation to get their analog-, RF-, and mixed-signal devices to market. Flavors of the venerable Spice simulator remain the tools of choice for analog ... read more |
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